Freescale Semiconductor MPC5200B - Manual (Page 685)

MPC5200B Users Guide, Rev. 1
20-6 Freescale Semiconductor
Memory Map and Registers
READ: any time
WRITE: IMSG, IE, and WCM any time.
CLKS write once in normal and emulation modes.
CLKS bit has modified functionality in special test mode.
Writes to unimplemented bits 5-2 are ignored.
IMSG — Ignore Message (Bit 7)
This bit allows the CPU to ignore messages by disabling updates of the BDLC State Vector Register register until a new Start of Frame
(SOF) or a BREAK symbol is detected. BDLC module transmitter and receiver operation are unaffected by the state of the IMSG bit.
1 = Disable BDLC State Vector Register Updates. When set, all BDLC interrupt sources (exceptions are described below) will be
prevented from updating BDLC State Vector Register status bits. Setting IMSG does not clear pending interrupt flags, the behavior
of which will still be as described in
Section , BDLC State Vector Register (DLCBSVR) . If this bit is set while the BDLC is receiving
or transmitting a message, state vector register updates will be inhibited for the rest of the message.
0 = Enable BDLC State Vector Register Updates. This bit is automatically cleared by the reception of a SOF symbol or a BREAK
symbol. It will then allow updates of the state vector register to occur.
There are two situations in which interrupts will not be masked by the IMSG bit: when a wakeup interrupt occurs; and when a receiver
error occurs which causes a byte pending transmission to be flushed from the transmit shadow register. See
Section 20.7.3.4, BDLC Data
Register (DLCBDR) - MBAR + 0x1305 for a description of the conditions which cause a pending transmission to be flushed.
CLKS
—
Clock Select (Bit 6)
The nominal BDLC operating frequency (mux interface clock frequency - f
bdlc
) must always be 1.048576 MHz or 1 MHz in order for
J1850 bus communications to take place properly. The CLKS register bit is provided to allow the user to indicate to the BDLC module
which frequency (1.048576 MHz or 1 MHz) is used so that each symbol time can be automatically adjusted.
The CLKS bit is a write once bit. All writes to this bit will be ignored after the first one.
Binary frequency (1.048576 MHz) is used for f
bdlc
.
Integer frequency (1 MHz) is used. for f
bdlc
Section 20.8.1.3, J1850 VPW Valid/Invalid Bits & Symbols describes the transmitter and receiver VPW symbol timing for integer and
binary frequencies.
IE
—
Interrupt Enable (Bit 1)
This bit determines whether the BDLC module will generate CPU interrupt requests. It does not affect CPU interrupt requests when
exiting the BDLC module Stop or Wait modes. Interrupt requests will be maintained until all of the interrupt request sources are cleared,
by performing the specified actions upon the BDLC module’s registers. Interrupts that were pending at the time that this bit is cleared
may be lost.
1 = Enable interrupt requests from BDLC module
0 = Disable interrupt requests from BDLC module
If the programmer does not wish to use the interrupt capability of the BDLC module, the BDLC State Vector Register (BDLC State Vector
Register) can be polled periodically by the programmer to determine BDLC module states. Refer to
Section 20.7.3.2, BDLC State Vector
Register (DLCBSVR) - MBAR + 0x1300 for a description of BDLC State Vector Register register and how to clear interrupt requests.
WCM
—
Wait Clock Mode (Bit 0) (Provided CPU has Low Power Mode Options)
This bit determines how the BDLC module responds when the CPU enters WAIT mode. As described in Section 20.3, Modes of
Operation , the BDLC module can respond by either entering BDLC_STOP mode, where all internal clocks are stopped, or entering
BDLC_WAIT mode where internal clocks are allowed to run.
Table 20-2. BDLC Control Register 1
msb 0 1 2 3 4 5 6 7 lsb
R IMSG CLKS 0 0 0 0 IE WCM
W
RESET: 1 1 0 0 0 0 0 0
= Unimplemented or Reserved