Freescale Semiconductor MPC5200B - Manual (Page 348)

Functional Description
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 10-51
10.4.2 Initiator Arbitration
There are three possible internal initiator sources - CommBus Transmit, CommBus Receive, or the XL bus (from Internal System Arbiter).
Custom interface logic arbitrates and provides mux select control for these sources to the PCI controller.
Figure 10-6 illustrates the arbitration
block connection.
Figure 10-6. Initiator Arbitration Block Diagram
10.4.2.1 Priority Scheme
The PCI Initiator arbiter uses the following fixed priority scheme.
1. XL bus Initiator
2. CommBus Transmit (Tx)
3. CommBus Receive (Rx) (lowest)
10.4.3 Configuration Interface
The PCI bus protocol requires the implementation of a standardized set of registers for most devices on the PCI bus. MPC5200B implements
a Type 0 Configuration register set or header. They are described in
Section 10.3.1, PCI Controller Type 0 Configuration Space . These
registers are primarily intended to be read or written by the PCI configuring master at initialization time through the PCI bus. MPC5200B
provides internal access to these registers through a Slave bus interface. As with most MPC5200B registers, they are accessible by software
in the address space at offsets of MBAR. Internal accesses to the Type 0 Configuration header do not require PCI arbitration when they are
accessed as offsets of MBAR and are allowed to execute regardless of whether any write data is posted in the PCI Controller.
If MPC5200B is the configuring master, the Slave bus interface should be used to configure the PCI Controller. An external master would
configure the PCI controller through the external PCI bus.
More information on the standard PCI Configuration register can be found in the PCI 2.2 specification.
10.4.4 XL bus Initiator Interface
The XL bus Initiator Interface provides access to the PCI bus for XL bus masters, primarily the processor core. This interface is accessed
through three windows in MPC5200B address space set up by base address and base address mask registers (
Section 10.3.2.5, Initiator
Window 0 Base/Translation Address Register PCIIW0BTAR(RW)—MBAR + 0x0D70 ). The base address registers must be enabled by setting
their respective Enable bits in the Section 10.3.2.8, Initiator Window Configuration Register PCIIWCR(RW) —MBAR + 0x0D80 . Accesses
to this area are translated into PCI transactions on the PCI bus. See Section 10.6.2, Address Maps for examples on setting up address windows.
The particular type of PCI transaction generated is determined by the PCI configuration bits associated with the address window (PCIIWCR).
For example, the user might set one window to do PCI memory read multiple accesses, one window for PCI I/O accesses, and the other
window to do non-prefetchable (memory-mapped I/O) PCI memory accesses.
Table 10-15 for command translation.
PCI Controller
Initiator
Interface
External
PCI bus
tx_gnt
PCI
request/grant
XL Bus
Arbiter
XL Bus
Initiator
Multi-Chan-
nel DMA
Controller
Bus
Initiator
Comm
PCI
Initiator
Arbiter
tx_req
rx_gnt
rx_req
(to PCI Arbiter)