Freescale Semiconductor MPC5200B - Manual (Page 602)

Overview
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 17-1
Chapter 17
Serial Peripheral Interface (SPI)
17.1 Overview
The following sections are contained in this document:
• Section 17.2, SPI Signal Description
• Section 17.3, SPI Registers—MBAR + 0x0F00
• Section 17.4, Functional Description
The Serial Peripheral Interface (SPI) allows full-duplex, synchronous, serial communication between the MPC5200B and peripheral devices.
Software can poll the SPI status flags or the SPI operation can be interrupt driven.
Figure 17-1 shows the SPI block diagram.
Figure 17-1. Block Diagram—SPI
17.1.1 Features
The SPI has the following features:
• Master mode and slave mode
• Bi-directional mode
• Slave-select output
• Mode fault error flag with CPU interrupt capability
• Double-buffered data register
• Serial clock with programmable polarity and phase
• Control of SPI operation during wait mode
8-BIT Shift Register
Read Data Buffer
Shift Control Logic
SPI Status Register
SPI Data Register
SPIF WCOL MODF
SPI Interrupt
IP bus
SPR2 SPR1 SPR0
Requ
est
SPIE SPE MSTR CPO
L
CPH
A
LS
B
F
E
LSBFE
SPISWAI SPC0 SWOM SSOE
SPE
Clock
MSTR
SWOM
Baud Rate Generator
S
PPR2
SPPR1 SPPR0
MISO
MOSI
SCK
SS
DIVIDER
2 4 8 16 32 64 128 256
SELECT
SPI Baud Rate Register
Clock
Logic
SPI Control Register 2 SPI Control Register 1
Pin Co
nt
rol Lo
gic
S
M
M
S
M
S
SP Control