Freescale Semiconductor MPC5200B - Manual (Page 43)

MPC5200B Users Guide, Rev. 1
1-8 Freescale Semiconductor
Architecture
1.2.5.5 Functional Pin Multiplexing
Many serial/parallel port pins serve multiple functions, allowing flexibility in optimizing the system to meet a specific set of integration
requirements. For example, when PSC3 interfaces to a full function external modem, 10 pins are required:
• PSC3_TXD—Transmit Data
• PSC3_RXD—Receive Data
• PSC3_ RTS —Ready to Send
• PSC3_ CTS —Clear to Send
• PSC3_CD—Carrier Detect
• MODEM_RI—Ring Indicator
• MODEM_DSR—Hook Switch
• MODEM_IO—Control I/O (A0 gain)
• MODEM_IO—Control I/O (Mode 1)
• MODEM_IO—Control I/O (Mode 2)
If PSC3 connects to a simple UART, only the first four signals (shown above) are required. The remaining 6 signals can be used as GPIOs.
If a 7-wire Ethernet connection is adequate, the additional 11 Ethernet I/Os can be used as GPIOs.
1.2.5.6 Real-Time Clock (RTC)
An RTC is included on the MPC5200B. The RTC provides a 2-pin interface to an external 32.768KHz crystal. This allows internal
time-of-day/calendar tracking, as well as clock based periodic interrupts.
1.2.6 SDRAM Controller and Interface
The MPC5200B high speed SDRAM Controller supports both standard SDRAM and Double Data Rate (DDR) SDRAM devices. It supports
up to 256MBytes per chip select (2 Chip Select lines available) with a 32-bit interface. Memory sizes of 64-Mbit, 128-Mbit, 256-Mbit and
512-Mbit are supported.
1.2.7 Multi-Function External LocalPlus Bus
The MPC5200B supports a multi-function external LocalPlus Bus to allow connections to PCI and ATA compliant devices, as well as external
ROM/SRAM.
The MPC5200B integrates a 3.3V, PCI V2.2 compatible external LocalPlus Bus controller and interface. This bus is a 32-bit multiplexed
address/data bus.
The external LocalPlus Bus provides support for an ATA disk drive interface. ATA control signals (chip selects, write/read, etc.) are provided
independent of the PCI control signals. This prevents bus contention. However, the 32-bit data bus is shared. When The MPC5200B
recognizes an external LocalPlus Bus access meant for the ATA Controller, ATA control logic arbitrates for PCI interface control. The 32-bit
address/data bus function is transformed into 16bits of ATA data and 3bits of ATA address.
The external LocalPlus Bus also allows connection to external memory or peripheral devices that adhere to a ROM or SRAM-like interface.
These devices occupy a separate location in the memory map and have independent control signals. When an internal access is decoded to
fall in the SRAM/ROM memory space, the 32-bit PCI address/data bus is transformed into either:
• 24bits of address and 8bits of data
• 16bits of address and 16bits of data.
The MPC5200B supports a reset configuration mode common on the family of processors that use the PowerPC architecture. 16 bits of
configuration information is driven and sampled during reset to establish the initial processor configuration.
1.2.8 Power Management
The MPC5200B is processed in a low-power static CMOS technology. In addition, it supports the dynamic power management modes
available on the MPC52xx series processors using the e300 core. These modes include:
• nap
• dose
• sleep
• deep sleep
In deep sleep, all internal clocks can be disabled, thus, reducing the power draw to CMOS leakage levels.