Freescale Semiconductor MPC5200B - Manual (Page 159)

MPC5200B Users Guide, Rev. 1
6-2 Freescale Semiconductor
e300 Core Reference Manual
6.3 e300 Core Reference Manual
A complete specification for the e300 core implementation used on the MPC5200B is obtained through a collection of documentation.
• PowerPC MicroprocessorFamily: The Programming Environments for 32-bit Microprocessors, Rev. 2: MPCFPE32B/AD
• G2 PowerPC Core Reference Manual, Rev. 1: G2CORERM/D
The programming environments manual provides information about resources defined by the PowerPC architecture that are common to
PowerPC processors. Implementation variances relative to Rev. 2 of the Programming Environments Manual are available in the G2 Core
Reference Manual.
The G2 Core Reference Manual can be obtained from the Freescale (formerly Motorola) Literature Distribution center at
http://e-www.freescale.com. Click on the Dovumentation link to proceed to the Semiconductor Documentation Library. In the documentation
form window, select “Reference Manual” and set the matching pages option button to “All”. An alphabetical list of refernce manuals will
appear and the G2 core document ID is ‘G2CORERM/D’. From this line entry, you may order hard copies of the G2 Core Reference Manual
or download a PDF copy of the manual.
6.4 Not supported e300 Core Features
6.4.1 Not supported instruction
The e300 core supports two instructions that are not available by the MPC5200B. These two instructions are eciowx and ecowx. The execution
of both instructions will generate a TEA signal on XLB. This will cause a machine check exception or a checkstop.
6.4.2 Not supported XLB parity feature
The e300 core supports an address and data parity error detection for the XL bus. This feature is not supported by the MPC5200B. The core
input signals core_ap_in [0:3] are pulled-down to 0 and the core input signals core_dp_in [0:7] are pulled-up to 1. Enabling of the address or
data parity error check by the HID0 [EBA, EBD] bits will generate a machine check exception or a checkstop depending on the HID0 [EMCP]
bit.