Fec physical address high register -23, Fec opcode/pause duration register -23, Section 14-23, fec physical address high register – Freescale Semiconductor MPC5200B User Manual
Page 488: Section 14-24, fec opcode/pause duration register
FEC Registers—MBAR + 0x3000
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
14-23
Note: X: Bit is not reset and must be initialized.
14.5.14
FEC Physical Address High Register—MBAR + 0x30E8
The PADDR2 register is written by the user. This register contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in the address
recognition process to compare with the destination address (DA) field of receive frames with an individual DA. In addition, this register is
used in Bytes 4 and 5 of the 6-Byte source address field when transmitting PAUSE frames. Bits 16:31 of XMIT.PADDR2 contain a constant
type field (hex 8808) used for transmission of PAUSE frames. This register is not reset and bits 0:15 must be initialized.
Note: X: Bit is not reset and must be initialized.
14.5.15
FEC Opcode/Pause Duration Register—MBAR + 0x30EC
The OP_PAUSE register is read/write accessible. This register contains the 16-bit opcode, and 16-bit pause duration fields used in
transmission of a PAUSE frame. The opcode field is a constant value, hex 0001. When another node detects a PAUSE frame, that node pauses
transmission for the duration specified in the pause duration field. This register is not reset and bits 16:31 must be initialized.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
PADDR1
W
RESET:
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bits
Name
Description
0:31
PADDR1
Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8) and 3 (bits 7:0) of the 6-byte individual
address used for an exact match, and the Source Address field in PAUSE frames.
Table 14-23. FEC Physical Address High Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
PADDR2
W
RESET:
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
TYPE
W
RESET:
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
Bits
Name
Description
0:15
PADDR2
Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for an exact match,
and the Source Address field in PAUSE frames.
16:31
TYPE
These 16 bits are a constant value, hex 8808.
Table 14-24. FEC Opcode/Pause Duration Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
OPCODE
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1