Freescale Semiconductor MPC5200B - Manual (Page 205)

MPC5200B Users Guide, Rev. 1
7-46 Freescale Semiconductor
General Purpose I/O (GPIO)
7.3.2.1.16 GPS GPIO Simple Interrupt Status Register—MBAR + 0x0B3C
Bit Name Description
0:2 — Reserved
3 ME GPIO Simple Interrupt Master Enable pin—This pin must be high before any Simple
Interrupt pin can generate an interrupt. This bit should remain clear while programming
individual interrupts, then set high as a final step. This prevents any spurious interrupt
occurring during programming.
4:31 — Reserved
Table 7-36. GPS GPIO Simple Interrupt Status Register
msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R ISTAT IVAL
W rwc rwc rwc rwc rwc rwc rwc rwc
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb
R Reserved
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Name Description
0:7 ISTAT Interrupt Status—status bit for GPIO Simple interrupt pins 7 to 0, where 1 indicates an
interrupt has occurred. Clear bit with a Sticky bit write to 1.
Bit 0 reflects GPIO_SINT_7 (ETH_16 pin)
Bit 1 reflects GPIO_SINT_6 (ETH_15 pin)
Bit 2 reflects GPIO_SINT_5 (ETH_14 pin)
Bit 3 reflects GPIO_SINT_4 (ETH_13 pin)
Bit 4 reflects GPIO_SINT_3 (USB1_9 pin)
Bit 5 reflects GPIO_SINT_2 (PSC3_8 pin)
Bit 6 reflects GPIO_SINT_1 (PSC3_5 pin)
Bit 7 reflects GPIO_SINT_0 (PSC3_4 pin)
8:15 IVAL Input Value—status bit for GPIO Simple Interrupt pins 7 to 0. This is the raw state of the
input pin at the time this register is read. It is not latched to the state that caused the
Interrupt (if any).
Bit 8 reflects GPIO_SINT_7 (ETH_16 pin)
Bit 9 reflects GPIO_SINT_6 (ETH_15 pin)
Bit 10 reflects GPIO_SINT_5 (ETH_14 pin)
Bit 11 reflects GPIO_SINT_4 (ETH_13 pin)
Bit 12 reflects GPIO_SINT_3 (USB1_9 pin)
Bit 13 reflects GPIO_SINT_2 (PSC3_8 pin)
Bit 14 reflects GPIO_SINT_1 (PSC3_5 pin)
Bit 15 reflects GPIO_SINT_0 (PSC3_4 pin)
IVAL is always available regardless of enable or setting, even if not used as GPIO.
Writing to this byte has no effect.
16:31 — Reserved