Freescale Semiconductor MPC5200B - Manual (Page 722)

Functional Description
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 20-43
Figure 20-17. Transmitting A Type 3 IFR
20.8.7 Receiving An In-Frame Response (IFR)
Receiving an In-Frame Response with the BDLC module is very similar to receiving a message frame. As each byte of an IFR is received,
the BDLC State Vector Register will indicate this to the CPU. An EOF indication in the BDLC State Vector Register indicates that the IFR
(and message) is complete. Also, the IMSG bit can also be used to command the BDLC module to mask any further network activity from
the CPU, including IFR bytes being received, until the next valid SOF is received.
Enter Type 3 IFR
Transmit Routine
Set desired
TMIFR bit in DLCBCR2
Is DLCBSVR = $00?
Yes
No
Load next byte to be
transmitted into DLCBDR
(clears TDRE)
Is DLCBSVR = $1C?
Yes
No
Is DLCBSVR = $14?
Yes
No
Is DLCBSVR = $10?
Yes
No
(TDRE)
(LOA)
(Invalid Symbol)
Is this the last
Yes
No
byte?
A
A
Jump to IFR
Receive Routine
Once BDLC module detects
EOF, IFR transmit
Set TEOD bit
in DLCBCR2
attempt is complete
Exit Type 3 IFR
Transmit Routine
B
B
Abandon IFR
transmit attempt
For interrupt driven systems,
this marks the beginning of the
transmit Type 3 IFR section of
the BDLC module interrupt
service routine
NOTE: The EOF and CRC Error interrupts
are handled in the IFR Receive Routine
Write first IFR
byte to be transmitted
into DLCBDR
Set TEOD bit in
Only one byte to
Yes
No
transmit? DLCBCR2