Ictl external enable and external types register – Freescale Semiconductor MPC5200B User Manual
Page 168
Interrupt Controller
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
7-9
7.2.4.5
ICTL External Enable and External Types Register —MBAR + 0x0510
8:11
Per18_pri
Peripheral 18 = CAN2
12:15
Per19_pri
Reserved
16:19
Per20_pri
Reserved
20:23
Per21_pri
Peripheral 21 = XLB Arbiter
24 :27
Per22_pri
Peripheral 22 = BDLC
28 :31
Per23_pri
Peripheral 23 = BestComm LocalPlus
Table 7-8. ICTL External Enable and External Types Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
ECLR(4)
Etype0
Etype1
Etype2
Etype3
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
MEE
EENA(4)
Reserved
CEb
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:3
—
Reserved
—
ECLR[x]
These bits clear external IRQ interrupt indications. When an IRQ input is configured as an
edge-sensitive input, the Interrupt Controller must be notified that the specific interrupt has
been serviced. Software must write 1 to the appropriate bit position to clear the interrupt
indication. ECLR bits are always read as 0 (i.e., they do not contain status).
4
ECLR0
IRQ[0], write 1 to clear
5
ECLR1
IRQ[1], write 1 to clear
6
ECLR2
IRQ[2], write 1 to clear
7
ECLR3
IRQ[3], write 1 to clear
8:9
Etype0
These bits control how the Interrupt Controller interprets the IRQ[0] input pin.
00 = Input is level sensitive and active hi
01 = Input is edge sensitive, rising edge active”
10 = Input is edge sensitive, falling edge active”
11 = Input is level sensitive, and active low”
10:11
Etype1
Same as above, but for the IRQ[1] input pin.
12:13
Etype2
Same as above, but for the IRQ[2] input pin.
14:15
Etype3
Same as above, but for the IRQ[3] input pin.
16:18
—
Reserved—unused bits, writing has no effect, always read as 0.
19
MEE
Master External Enable—clearing this bit masks all IRQ input transitions (including status
indications).
Bits
Name
Description