Gpw wakeup gpio open drain emulation register, Gpw wakeup gpio data direction register – Freescale Semiconductor MPC5200B User Manual
Page 207
MPC5200B Users Guide, Rev. 1
7-48
Freescale Semiconductor
General Purpose I/O (GPIO)
7.3.2.2.2
GPW WakeUp GPIO Open Drain Emulation Register —MBAR + 0x0C04
7.3.2.2.3
GPW WakeUp GPIO Data Direction Register—MBAR + 0x0C08
Table 7-38. GPW WakeUp GPIO Open Drain Emulation Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
WODe
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description
0:7
WODe
Bits to control open drain emulation for individual WakeUp GPIO configured as outputs.
Bit 0 controls GPIO_WKUP_7 (GPIO_WKUP_7 pin)
Bit 1 controls GPIO_WKUP_6 (GPIO_WKUP_6 pin)
Bit 2 controls GPIO_WKUP_5 (PSC6_1 pin)
Bit 3 controls GPIO_WKUP_4 (PSC6_0 pin)
Bit 4 controls GPIO_WKUP_3 (ETH_17 pin)
Bit 5 controls GPIO_WKUP_2 (PSC3_9 pin)
Bit 6 controls GPIO_WKUP_1 (PSC2_4 pin)
Bit 7 controls GPIO_WKUP_0 (PSC1_4 pin)
0 = Normal CMOS output (default).
1 = Open Drain emulation (a drive to high creates Hi-Z).
8:31
—
Reserved
Table 7-39. GPW WakeUp GPIO Data Direction Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
WDDR[7:0]
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0