Freescale Semiconductor MPC5200B - Manual (Page 741)

MPC5200B Users Guide, Rev. 1
A-2 Freescale Semiconductor
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BIP . . . . . . . . . . . . . . . . . . . . Bit Interleaved Parity
BIST . . . . . . . . . . . . . . . . . . . Built-In Self Test
BISYNC . . . . . . . . . . . . . . . . Binary Synchronous communication
Blockage . . . . . . . . . . . . . . . . A pipeline stall that occurs when an instruction occupies an execution unit and prevents a subsequent instruction
from being dispatched.
Boundedly undefined . . . . . . A characteristic of certain operations results not rigidly prescribed by the PowerPC architecture. Boundedly
undefined results for a given operation may vary among implementations, and between execution attempts in
the same implementation.
Although the architecture does not prescribe the exact behavior for when results are allowed to be boundedly undefined, the results of
executing instructions in contexts where results are allowed to be boundedly undefined are constrained to ones
that could have been achieved by executing an arbitrary sequence of defined instructions, in valid form, starting
in the state the machine was in before attempting to execute the given instruction.
bps. . . . . . . . . . . . . . . . . . . . . bits per second
BPU. . . . . . . . . . . . . . . . . . . . Branch Processing Unit
BR . . . . . . . . . . . . . . . . . . . . . Bus Request
BRC . . . . . . . . . . . . . . . . . . . Backward Reporting Cells
Breakpoint. . . . . . . . . . . . . . . A programmable event that forces the core to take a breakpoint exception.
BT . . . . . . . . . . . . . . . . . . . . . Burst Tolerance
BUID. . . . . . . . . . . . . . . . . . . Bus Unit ID
Burst . . . . . . . . . . . . . . . . . . . A bus transfer whose data phase consists of a sequence of transfers. For example, on a 64-bit bus, a four-beat
burst can transfer four, 64-bit double words.
Bus parking . . . . . . . . . . . . . . A feature that optimizes bus usage by letting a device retain bus mastership without having to rearbitrate.
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Cache . . . . . . . . . . . . . . . . . . High-speed memory component containing recently accessed data and/or instructions (subset of main
memory).
Cache coherency . . . . . . . . . . An attribute in which an accurate and common view of memory is provided to all devices that share a memory
system. Caches are coherent if a processor performing a read from its cache is supplied with data corresponding
to the most recent value written to memory or to another processor’s cache.
Cache flush . . . . . . . . . . . . . . An operation that removes from a cache any data from a specified address range. This operation ensures any
modified data within the specified address range is written back to main memory. This operation is generated
typically by a Data Cache Block Flush (dcbf) instruction.
Caching-inhibited . . . . . . . . . A memory update policy in which the cache is bypassed and the load or store is done to or from main memory.
CAM . . . . . . . . . . . . . . . . . . . Content Addressable Memory
CAN . . . . . . . . . . . . . . . . . . . Controller Area Network
Cast-outs . . . . . . . . . . . . . . . . Cache blocks that must be written to memory when a cache miss causes a cache block to be replaced.
CBR . . . . . . . . . . . . . . . . . . . Constant Bit-Rate. See also UBR and ABR.
CD. . . . . . . . . . . . . . . . . . . . . Carrier Detect
CDM . . . . . . . . . . . . . . . . . . . Clock Distribution Module
CDV . . . . . . . . . . . . . . . . . . . Cell Delay Variation
CEPT. . . . . . . . . . . . . . . . . . . Conference des administrations Europeanes des Postes et Telecommunications (European Conference of Postal
and Telecommunications Administrations).
CES . . . . . . . . . . . . . . . . . . . . Circuit Emulation Service
cfg . . . . . . . . . . . . . . . . . . . . . configuration
Changed bit . . . . . . . . . . . . . . One of two page history bits found in each page table entry (PTE). The processor sets the changed bit if any
store is performed into the page. See also Page access history bits and Referenced bit.
C/I. . . . . . . . . . . . . . . . . . . . . Condition/Indication (channel used in GCI protocol)
Clear . . . . . . . . . . . . . . . . . . . To cause a bit or bit field to register a value of 0. The opposite of set.
CLP . . . . . . . . . . . . . . . . . . . . Cell Loss Priority
cmd . . . . . . . . . . . . . . . . . . . . command
cnt . . . . . . . . . . . . . . . . . . . . . count
CODEC. . . . . . . . . . . . . . . . . COder/DECoder, or COmpression/DECommpression