Chapter 10 pci controller, 1 overview, 1 features – Freescale Semiconductor MPC5200B User Manual
Page 298: Chapter 10, pci controller
Overview
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
10-1
Chapter 10
PCI Controller
10.1
Overview
The Peripheral Component Interface (PCI) Bus is a high-performance bus with multiplexed address and data lines. It is especially suitable for
high data-rate applications.
The MPC5200B PCI Controller module supports a 32-bit PCI initiator and target interface. As a target, access to the internal XL bus is
supported. As an initiator, the PCI controller is coupled directly to the XL bus (as a slave) and available on the Communication Sub-System
as a Multi-Channel DMA peripheral.
The 32-bit multiplexed address/data is shared with the ATA Controller and LocalPlus Controllers. However, control signals are on separate
pins and only one operation (PCI, ATA, or LocalPlus) can be done at any given time.
The LocalPlus Large Flash and Most/Graphic interfaces are not compatible with any PCI operation. When these interfaces are needed, the
PCI internal controller must be disabled by setting bit 16 (PCI_DIS) of the GPS Configuration register.
Configuration Register—MBAR + 0x0B00
The MPC5200B contains PCI central resource functions such as the PCI Arbiter (
) and PCI reset control. The PCI
bus clock is always sourced from the MPC5200B and either equal to 1, 1/2 the frequency of the Slave bus clock (IP bus clock) or 1/4 the
frequency of the XL Bus clock. Even when the PCI internal controller is disabled, the PCI clock is sourced by the MPC5200B.
A PCI reset signal is provided and implemented as an open-drain pin. An external (on board) pull-up resistor (e.g. 5.6 kOhm) is then required
to ensure proper operation.
NOTE
If the PCI interface is NOT used (and internally disabled) the PCI control pins must be terminated as
indicated by the PCI Local Bus specification. PCI control signals always require pull-up resistors to
ensure that they contain stable values when no agent is actively driving the bus. This includes
PCI_FRAME, PCI_TRDY, PCI_IRDY, PCI_DEVSEL, PCI_STOP, PCI_SERR, PCI_PERR, and
PCI_REQ.
10.1.1
Features
•
Supports system clock: Slave (IP) bus (internal peripheral slave bus) to PCI bus frequency ratios 1:1, 2:1. Or the XL Bus to PCI bus
frequency ratio 4:1 (e.g. PCI runs at 33 MHz while the XL Bus bus runs at 132 MHz).
•
Compatible with PCI 2.2 specification
•
PCI initiator and target operation
•
Fully synchronous design
•
32-bit PCI Address/Data bus
•
PCI 2.2 Type 0 Configuration Space header
•
Supports the PCI 16/8 clock rule
•
PCI master Multi-Channel DMA or CPU access to PCI Bus
•
High transfer rates at 66Mhz PCI clock, 512 byte buffer
•
PCI to system bus address translation
•
Target response is medium DEVSEL generation
•
Initiator latency time-outs are NOT supported.
•
Automatic retry of target disconnects
•
Fast Back-to-Back transactions are NOT supported.
NOTE
The corresponding FC bit in the Configuration Status Register is fixed to ‘1’ indicating the opposite.
Nonetheless no Fast Back-to-Back transaction is supported.