Freescale Semiconductor MPC5200B - Manual (Page 753)

MPC5200B Users Guide, Rev. 1
B-2 Freescale Semiconductor
7.3.2.1.13 GPS GPIO Simple Interrupt Interrupt Enable Register —MBAR + 0x0B30 ...................................... 8-44
7.3.2.1.14 GPS GPIO Simple Interrupt Interrupt Types Register —MBAR + 0x0B34........................................ 8-45
7.3.2.1.15 GPS GPIO Simple Interrupt Master Enable Register —MBAR + 0x0B38 ......................................... 8-45
7.3.2.1.16 GPS GPIO Simple Interrupt Status Register—MBAR + 0x0B3C....................................................... 8-46
Section
7.3.2.2 WakeUp GPIO Registers—MBAR+0x0C00............................................................................................. 8-47
7.3.2.2.1 GPW WakeUp GPIO Enables Register—MBAR + 0x0C00 ............................................................... 8-47
7.3.2.2.2 GPW WakeUp GPIO Open Drain Emulation Register —MBAR + 0x0C04....................................... 8-48
7.3.2.2.3 GPW WakeUp GPIO Data Direction Register—MBAR + 0x0C08 .................................................... 8-48
7.3.2.2.4 GPW WakeUp GPIO Data Value Out Register —MBAR + 0x0C0C.................................................. 8-49
7.3.2.2.5 GPW WakeUp GPIO Interrupt Enable Register—MBAR + 0x0C10 .................................................. 8-50
7.3.2.2.6 GPW WakeUp GPIO Individual Interrupt Enable Register —MBAR + 0x0C14................................ 8-50
7.3.2.2.7 GPW WakeUp GPIO Interrupt Types Register—MBAR + 0x0C18.................................................... 8-51
7.3.2.2.8 GPW WakeUp GPIO Master Enables Register —MBAR + 0x0C1C.................................................. 8-52
7.3.2.2.9 GPW WakeUp GPIO Data Input Values Register —MBAR + 0x0C20 .............................................. 8-53
7.3.2.2.10 GPW WakeUp GPIO Status Register—MBAR + 0x0C24 .................................................................. 8-54
Section 7.4.4 GPT Registers—MBAR + 0x0600............................................................................................................. 8-56
7.4.4.1 GPT 0 Enable and Mode Select Register—MBAR + 0x0600.............................................................. 8-56
7.4.4.2 GPT 0 Counter Input Register—MBAR + 0x0604 .............................................................................. 8-59
7.4.4.3 GPT 0 PWM Configuration Register—MBAR + 0x0608.................................................................... 8-60
7.4.4.4 GPT 0 Status Register—MBAR + 0x060C .......................................................................................... 8-61
Section 7.5.1 SLT Registers—MBAR + 0x0700 ............................................................................................................. 8-62
7.5.1.1 SLT 0 Terminal Count Register—MBAR + 0x0700 ............................................................................ 8-63
7.5.1.2 SLT 0 Control Register—MBAR + 0x0704 ......................................................................................... 8-63
7.5.1.3 SLT 0 Count Value Register—MBAR + 0x0708 ................................................................................. 8-64
7.5.1.4 SLT 0 Timer Status Register—MBAR + 0x070C ................................................................................ 8-65
Section 7.6.3 RTC Interface Registers—MBAR + 0x0800 ............................................................................................. 8-66
7.6.3.1 RTC Time Set Register—MBAR + 0x0800 ......................................................................................... 8-67
7.6.3.2 RTC Date Set Register—MBAR + 0x0804.......................................................................................... 8-68
7.6.3.3 RTC New Year and Stopwatch Register—MBAR + 0x0808............................................................... 8-69
7.6.3.4 RTC Alarm and Interrupt Enable Register—MBAR + 0x080C........................................................... 8-69
7.6.3.5 RTC Current Time Register—MBAR + 0x0810.................................................................................. 8-70
7.6.3.6 RTC Current Date Register—MBAR + 0x0814................................................................................... 8-71
7.6.3.7 RTC Alarm and Stopwatch Interrupt Register—MBAR + 0x0818...................................................... 8-71
7.6.3.8 RTC Periodic Interrupt and Bus Error Register—MBAR + 0x081C ................................................... 8-72
7.6.3.9 RTC Test Register/Divides Register—MBAR + 0x0820..................................................................... 8-73
Section 8.7 Memory Controller Registers (MBAR+0x0100:0x010C) ......................................................................... 8-20
8.7.1 Mode Register—MBAR + 0x0100....................................................................................................... 8-20
8.7.2 Control Register—MBAR + 0x0104.................................................................................................... 8-22
8.7.3 Configuration Register 1—MBAR + 0x0108 ...................................................................................... 8-25
8.7.4 Configuration Register 2—MBAR + 0x010C...................................................................................... 8-27
Section 9.7.1 Chip Select/LPC Registers—MBAR + 0x0300 .........................................................................................9-11
9.7.1.1 Chip Select 0/Boot Configuration Register—MBAR + 0x0300 .......................................................... 9-13
9.7.1.2 Chip Select 1 Configuration Register—MBAR + 0x0304................................................................... 9-15
9.7.1.3 Chip Select Control Register—MBAR + 0x0318 ................................................................................ 9-17
9.7.1.4 Chip Select Status Register—MBAR + 0x031C .................................................................................. 9-18
9.7.1.5 Chip Select Burst Control Register—MBAR + 0x0328 ...................................................................... 9-18
9.7.1.6 Chip Select Deadcycle Control Register—MBAR + 0x032C.............................................................. 9-21