Freescale Semiconductor MPC5200B - Manual (Page 668)

Functional Description
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 19-29
flag, and generates a receive interrupt Section 19.7.9.2, Receive Interrupt to the CPU 1 . The user’s receive handler has to read the received
message from the RxFG and then reset the RXF flag to acknowledge the interrupt and to release the foreground buffer. A new message, which
can follow immediately after the IFS field of the CAN frame, is received into the next available RxBG. If the MSCAN receives an invalid
message in its RxBG (wrong identifier, transmission errors etc.) the actual contents of the buffer will be over-written by the next message.
The buffer will then not be shifted into the FIFO.
When the MSCAN module is transmitting, the MSCAN receives its own transmitted messages into the background receive buffer, RxBG, but
does not shift it into the receiver FIFO, generate a receive interrupt, or acknowledge its own messages on the CAN bus. The exception to this
rule is in loop back mode
Section 19.5.4, MSCAN Control Register 1 (CANCTL1)—MBAR + 0x0901 / 0x981 where the MSCAN treats its
own messages exactly like all other incoming messages. The MSCAN receives its own transmitted messages in the event that it loses
arbitration
2 . If arbitration is lost, the MSCAN must be prepared to become a receiver.
An overrun condition occurs when all receive message buffers in the FIFO are filled with correctly received messages with accepted identifiers
and another message is correctly received from the bus with an accepted identifier. The latter message is discarded and an error interrupt with
overrun indication is generated if enabled
Section 19.7.9.4, Error Interrupt . The MSCAN is still able to transmit messages while the receiver
FIFO being filled, but all incoming messages are discarded. As soon as a receive buffer in the FIFO is available again, new valid messages
will be accepted.
19.7.3 Identifier Acceptance Filter
The MSCAN Identifier Acceptance Registers ( Section 19.5.14, MSCAN ID Acceptance Control Register (CANIDAC)—MBAR + 0x0915 /
0x0995 ) define the acceptable patterns of the standard or extended identifier (ID10 - ID0 or ID28 - ID0). Any of these bits can be marked
‘don’t care’ in the MSCAN Identifier Mask Registers Section 19.5.18, MSCAN ID Mask Register (CANIDMR0-7)—MBAR + 0x0928 /
0x09A8 .
A filter hit is indicated to the application software by a set Receive Buffer Full flag (RXF=1) and three bits in the CANIDAC register Section
19.5.17, MSCAN ID Acceptance Registers (CANIDAR0-7)—MBAR + 0x0920 / 0x09A0 . These Identifier Hit flags (IDHIT2-0) clearly identify
the filter section that caused the acceptance. They simplify the application software’s task to identify the cause of the receiver interrupt. In
case more than one hit occurs (two or more filters match), the lower hit has priority.
A very flexible programmable generic identifier acceptance filter has been introduced to reduce the CPU interrupt loading. The filter is
programmable to operate in four different modes
3 :
• Two identifier acceptance filters, each to be applied to a) the full 29 bits of the extended identifier and to the following bits of
the CAN 2.0B frame: Remote Transmission Request (RTR), Identifier Extension (IDE), and Substitute Remote Request
(SRR) or b)
4 the 11 bits of the standard identifier plus the RTR and IDE bits of the CAN 2.0A/B messages. This mode
implements two filters for a full length CAN 2.0B compliant extended identifier. Figure 19-4 shows how the first 32-bit filter
bank (CANIDAR0-3, CANIDMR0-3) produces a filter 0 hit. Similarly, the second filter bank (CANIDAR4-7, CANIDMR4-7)
produces a filter 1 hit.
• Four identifier acceptance filters, each to be applied to a) the 14 most significant bits of the extended identifier plus the SRR
and IDE bits of CAN 2.0B messages or b) the 11 bits of the standard identifier, the RTR and IDE bits of CAN 2.0A/B
messages.
Figure 19-5 shows how the first 32-bit filter bank (CANIDAR0-3, CANIDMR0-3) produces filter 0 and 1 hits.
Similarly, the second filter bank (CANIDAR4-7, CANIDMR4-7) produces filter 2 and 3 hits.
• Eight identifier acceptance filters, each to be applied to the first 8 bits of the identifier. This mode implements eight
independent filters for the first 8 bits of a CAN 2.0A/B compliant standard identifier or a CAN 2.0B compliant extended
identifier.
Figure 19-6 shows how the first 32-bit filter bank (CANIDAR0-3, CANIDMR0-3) produces filter 0 to 3 hits. Similarly,
the second filter bank (CANIDAR4-7, CANIDMR4-7) produces filter 4 to 7 hits.
• Closed filter. No CAN message is copied into the foreground buffer RxFG, and the RXF flag is never set.
1. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also.
2. Reference the Bosch CAN 2.0A/B protocol specification dated September 1991 for details.
3. For a better understanding of references made within the filter mode description, reference the Bosch specification dated September 1991
which details the CAN 2.0A/B protocol.
4. Although this mode can be used for standard identifiers, it is recommended to use the four or eight identifier acceptance filters for standard
identifiers