15 ac97 slots register (0x24)-ac97slots, 16 ac97 command register (0x28)-ac97cmd, Ac97 slots register (0x24)—ac97slots – Freescale Semiconductor MPC5200B User Manual
Page 537: Ac97 command register (0x28)—ac97cmd, Ac97cmd, Ac97slots
MPC5200B Users Guide, Rev. 1
15-26
Freescale Semiconductor
PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
15.2.15
AC97 Slots Register (0x24)—AC97Slots
This write only register defines which slots are expected in a receive AC97 frame and which slots will be send in a AC97 TX frame. If the
received frame doesn’t match the expected slots the
[UNEXP_RX_SLOTS] bit will be set. This register has affect only if the and AC97
register and if the EnAC97 bit is active.
Table 15-35. AC97 Slots Register (0x24)—AC97Slots
15.2.16
AC97 Command Register (0x28)—AC97CMD
This register contains the AC97 address for transmit slot1 and the AC97 command data for transmit slot 2. A write access to any byte of this
register will set the
[CMD_SEND] bit to one. The AC97 transmitter generate a frame with valid slot1 and slot2 and paste the values of this
register to the next transmitted slot1 and slot2. If the data was send, then the
[CMD_SEND] bit will be cleared by the transmitter.
Table 15-36. AC97 Command Register (0x28)—AC97CMD
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 lsb
R
Reserved
W
Reserved
TX_Slots[3:12]
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Reserved
W
Reserved
RX_Slots[3:12]
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description
0:5
—
Reserved
6:15
TX_Slots[3:12]
Enhanced AC97 Mode—Expected Receive Slots
The bits in this register specifies which data slots [3:12] will be send in an AC97 TX
frame. The AC97 transmitter will use this information to generate the Slot0 and will
read out the according number of data words from the TXFIFO. If the TXFIFO is
empty an empty AC97 frame will be send until new data are available.
other Modes—Reserved
16:21
—
Reserved
22:3‘
RX_Slots[3:12]
Enhanced AC97 Mode—Expected Receive Slots
The bits in this register specifies which data slots [3:12] in the receive AC97 frame
must contain valid data. The AC97 Codec select the valid data slots by setting the
according data valid bit in Slot0[12:3]. If the received valid slots not match the
expected slots the “Unexpected Slot Received” state occurred. See register
Only if the received slots matched the expected slots the received data will be written
to the RXFIFO. If the Receiver detect an AC97 frame without data (Frame is empty
or contains only status data) the “Unexpected Slot Received” state will not occurred.
other Modes—Reserved
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 lsb
R
A97
CMD
AC97 Control Register Index
AC97 Command Data[15:8]
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
AC97 Command Data[7:0]
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0