Freescale Semiconductor MPC5200B - Manual (Page 391)

MPC5200B Users Guide, Rev. 1
11-26 Freescale Semiconductor
ATA Bus Background
Figure 11-3. Pin Description—ATA Interface
11.7 ATA Bus Background
11.7.1 Terminology
The most popular interface used in modern hard disks is the Integrated Drive Electronics (IDE) interface, also known by various other names
such as: ATA, EIDE, ATA-2, Fast ATA, Ultra ATA, etc.
• Western Digital ® used the term IDE when they first integrated the drive controller logic board on the disk drive.
• Quantum ® and Seagate ® used the term ATA (Advanced Technology Attachment) or AT-Attachment, because it has a 16-bit data
interface like original AT machines.
ATA is the interface name adopted by the American National Standards Institute (ANSI). Thus far, ANSI has published ATA, ATA-2, ATA-3
and ATA-4 interfaces. More work is underway for ATA-5 and future extensions of the ATA interface.
Table 11-35 summarizes the different
ATA standards.
MPC5200B is compliant with the latest officially published ANSI ATA-4 interface.
DIOR:HDMARDY:HSTROBE DIOR →Asserted by host to read drive registers or data ports.
HDMARDY →Host ready to receive UDMA data in bursts. Negated to pause.
HSTROBE →Host signal for UDMA data out bursts. Data latched in drive registers from DD[15:0]
on both edges of HSTROBE. Host stops generating HSTROBE edges to pause.
DD[15:0] 8-, 16-bit data interface.
DA[2:0] Address to access drive registers or data ports.
CS[0], CS[1] Chip Select to select Command Block registers.
DIOW:STOP DIOW →Asserted by host to write drive registers or data ports. Negated by host before initiation of UDMA.
STOP →Negated by host before UDMA burst. Assertion by host signals termination of UDMA.
DMACK Host response to DMARQ by drive to initiate DMA transfers.
DMARQ Asserted by drive for DMA data transfers from/to host. For multiword DMA, data direction is
controlled by DIOR and DIOW. MARQ is negated by drive when DMACK is received from
host.drivere-asserts DMARQ for more DMA transfers.
INTRQ INTRQ used by selected drive to interrupt host. If (nIEN bit == 0 && drive is selected),
INTRQ must be enabled through tri-state and must be driven asserted or negated.
If (nIEN == 1 || drive is not selected), INTRQ = 1'bz.
When INTRQ asserted, drive must negate it within 400ns of negation of DIOR that reads
STATUS register or within 400ns of negation of DIOW that writes the COMMAND register.
When drive is selected by writing to Device/Head register and interrupt is pending, INTRQ
must be asserted within 400ns of negation of DIOW that writes the Device/Head register.
When drive is de-selected by writing to Device/Head register and interrupt is pending, INTRQ
must be negated within 400ns of negation of DIOW that writes the Device/Head register.
IORDY:DDMARDY:DSTROBE IORDY is negated by drive to extend host transfer cycle (read or write) for PIO modes 3 and above.
DDMARDY →drive ready to receive UDMA data out bursts. Negated to pause.
DSTROBE →drive signal from UDMA data in bursts. Data latched in host registers from
DD[15:0] on both edges of DSTROBE. Drive stops generating DSTROBE edges to pause.
PDIAG:CBLID PDIAG →is asserted by drive 1 to indicate to drive 0 that it has completed diagnostics.
CBLID →Host may sample CBLID after Power-ON or hardware reset is completed for all drives on
the cable, to detect presence or absence of 80 conductor cable. If CBLID is detected as connected
to ground then 80-conductor cable is present.
If drive 1 is present, Host should issue IDENTIFY DEVICE or IDENTIFY PACKET DEVICE
and use returned data to determine if drive is compliant with ATA-3 or subsequent standards.
Drives compliant with ATA-3 or above, release PDIAG no later than after the first command
following a Power-ON or hardware reset sequence.
RESET RESET used by host to reset drive.
CSEL CSEL negated, drive address is 0
CSEL asserted, drive address is 1
H O S T D E V I C E