Freescale Semiconductor MPC5200B - Manual (Page 216)

General Purpose Timers (GPT)
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 7-57
Bit Name Description
0:7 OCPW Output Compare Pulse Width—Applies to OC Pulse types only. This field specifies the number
of IP bus clocks (non-prescaled) to create a short output pulse at each Output Event. This
pulse is generated at the end of the OC period and overlays the next OC period (rather than
adding to the period).
Note: This field is alternately used as the Watchdog reset field if Watchdog Timer mode is
enabled.
8:9 — Reserved
10:11 OCT Output Compare Type—describes action to occur at each output compare event, as follows:
00=Special case, output is immediately forced low without respect to each output compare
event.
01=Output pulse highs, initial value is low (OCPW field applies).
10=Output pulses low, initial value is high (OCPW field applies).
11=Output toggles.
GPIO modalities can be used to achieve an initial output state prior to enabling OC mode. It is
important to move directly from GPIO output mode to OC mode and not to pass through the
Timer_MS=000 state.
To prevent the Internal Timer Mode from engaging during the GPIO state, CE bit should be
held low during the configuration steps.
GPIO initialization is needed when presetting the I/O to 1 in conjunction with a simple toggle
OCT setting.
Note: For Stop Mode operation (see Stop_Cont bit below) it is necessary to pass through the
mode_sel = 0 state to restart the output compare counters with their programmed values. See
prescale and count fields in
GPT 0 Counter Input Register .
12:13 — Reserved
14:15 ICT Input Capture Type—describes the input transition type required to trigger an input capture
event, as follows:
00=Any input transition causes an IC event.
01=IC event occurs at input rising edge.
10=IC event occurs at input falling edge.
11=IC event occurs at any input pulse (i.e., at 2nd input edge).
BE AWARE: For ICT=11 (pulse capture), status register records only the pulse width.
16 WDen Watchdog enable—bit enables watchdog operation. A timer expiration causes an internal
MPC5200B reset. Watchdog operation requires the Timer_MS field be set for internal timer
mode and the CE bit to be set high.
In this mode the OCPW byte field operates as a watchdog reset field. Writing A5 to the OCPW
field resets the watchdog timer, preventing it from expiring. As long as the timer is properly
configured, the watchdog operation continues.
This bit (and functionality) is implemented only for Timer 0. 1 = enabled
17:18 — Reserved
19 CE Counter Enable—bit enables or resets the internal counter during Internal timer modes only.
CE must be high to enable these modes. If low, counter is held in reset.
This bit is secondary to the timer mode select bits (Timer_MS). If Timer_MS is1XX, internal
timer modes are enabled. CE can then enable or reset the internal counter without changing
the Timer_MS field.
GPIO operation is also available in this mode. 1 = enabled
20 — Reserved