Fec descriptor individual address 1 register -24, Fec descriptor individual address 2 register -24 – Freescale Semiconductor MPC5200B User Manual
Page 489
MPC5200B Users Guide, Rev. 1
14-24
Freescale Semiconductor
FEC Registers—MBAR + 0x3000
Note: X: Bit is not reset and must be initialized.
14.5.16
FEC Descriptor Individual Address 1 Registe—MBAR + 0x3118
The IADDR1 register is written by the user. This register contains the upper 32 bits of the 64-bit individual address hash table used in the
address recognition process to check for possible match with the DA field of receive frames with an individual DA. This register is not reset
and must be initialized.
Note: X: Bit is not reset and must be initialized.
14.5.17
FEC Descriptor Individual Address 2 Register—MBAR + 0x311C
The IADDR2 register is written by the user. This register contains the lower 32 bits of the 64-bit individual address hash table used in the
address recognition process to check for possible match with the DA field of receive frames with an individual DA. This register is not reset
and must be initialized.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
PAUSE_DUR
W
RESET:
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bits
Name
Description
0:15
OPCODE
Opcode field used in PAUSE frames. Bits are a constant value, hex 0001.
16:31
PAUSE_DUR
Pause Duration field used in PAUSE frames.
Table 14-25. FEC Descriptor Individual Address 1 Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
IADDR1
W
RESET:
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
IADDR1
W
RESET:
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bits
Name
Description
0:31
IADDR1
The upper 32 bits of the 64-bit hash table used in the address recognition process for receive
frames with a unicast address.
• Bit 31 contains hash index bit 63.
• Bit 0 contains hash index bit 32.
Table 14-26. FEC Descriptor Individual Address 2 Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
IADDR2
W
RESET:
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X