Freescale Semiconductor MPC5200B - Manual (Page 18)

Table of Contents
Paragraph Page
Number Number
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor TOC-17
Chapter 20 Byte Data Link Controller (BDLC)
20.1 Overview .................................................................................................................................................................20-1
20.2 Features ...................................................................................................................................................................20-1
20.3 Modes of Operation .................................................................................................................................................20-1
20.4 Block Diagram ........................................................................................................................................................20-4
20.5 Signal Description ...................................................................................................................................................20-5
20.6 Overview .................................................................................................................................................................20-5
20.6.1 Detailed Signal Descriptions .............................................................................................................................20-5
20.6.1.1 TXB - BDLC Transmit Pin ........................................................................................................................20-5
20.6.1.2 RXB - BDLC Receive Pin ..........................................................................................................................20-5
20.7 Memory Map and Registers ....................................................................................................................................20-5
20.7.1 Overview ...........................................................................................................................................................20-5
20.7.2 Module Memory Map .......................................................................................................................................20-5
20.7.3 Register Descriptions ........................................................................................................................................20-5
20.7.3.1 BDLC Control Register 1 (DLCBCR1)—MBAR + 0x1300 .....................................................................20-5
20.7.3.2 BDLC State Vector Register (DLCBSVR) - MBAR + 0x1300 .................................................................20-7
20.7.3.3 BDLC Control Register 2 (DLCBCR2) - MBAR + 0x1304 ......................................................................20-8
20.7.3.4 BDLC Data Register (DLCBDR) - MBAR + 0x1305 .............................................................................20-12
20.7.3.5 BDLC Analog Round Trip Delay Register (DLCBARD) - MBAR + 0x1308 ........................................20-12
20.7.3.6 BDLC Rate Select Register (DLCBRSR) - MBAR + 0x1309 .................................................................20-14
20.7.3.7 BDLC Control Register (DLCSCR) - MBAR + 0x130C .........................................................................20-15
20.7.3.8 BDLC Status Register (DLCBSTAT) - MBAR + 0x130D ......................................................................20-15
20.8 Functional Description ..........................................................................................................................................20-16
20.8.1 General ............................................................................................................................................................20-16
20.8.1.1 J1850 Frame Format .................................................................................................................................20-16
20.8.1.2 J1850 VPW Symbols ................................................................................................................................20-17
20.8.1.3 J1850 VPW Valid/Invalid Bits & Symbols ..............................................................................................20-19
20.8.1.4 J1850 Bus Errors ......................................................................................................................................20-26
20.8.2 Mux Interface ..................................................................................................................................................20-27
20.8.2.1 Mux Interface - Rx Digital Filter ..............................................................................................................20-27
20.8.3 Protocol Handler .............................................................................................................................................20-28
20.8.3.1 Protocol Architecture ................................................................................................................................20-29
20.8.4 Transmitting A Message ................................................................................................................................20-30
20.8.4.1 BDLC Transmission Control Bits ............................................................................................................20-30
20.8.4.2 Transmitting Exceptions ...........................................................................................................................20-31
20.8.4.3 Aborting a Transmission ..........................................................................................................................20-32
20.8.5 Receiving A Message ....................................................................................................................................20-33
20.8.5.1 BDLC Reception Control Bits ..................................................................................................................20-34
20.8.5.2 Receiving a Message with the BDLC module ..........................................................................................20-34
20.8.5.3 Filtering Received Messages ....................................................................................................................20-34
20.8.5.4 Receiving Exceptions ...............................................................................................................................20-34
20.8.6 Transmitting An In-Frame Response (IFR) ...................................................................................................20-36
20.8.6.1 IFR Types Supported by the BDLC module ............................................................................................20-37
20.8.6.2 BDLC IFR Transmit Control Bits ............................................................................................................20-37
20.8.6.3 Transmit Single Byte IFR .........................................................................................................................20-38
20.8.6.4 Transmit Multi-Byte IFR 1 .......................................................................................................................20-38
20.8.6.5 Transmit Multi-Byte IFR 0 .......................................................................................................................20-38
20.8.6.6 Transmitting An IFR with the BDLC module ..........................................................................................20-38
20.8.6.7 Transmitting IFR Exceptions ....................................................................................................................20-42
20.8.7 Receiving An In-Frame Response (IFR) .......................................................................................................20-43
20.8.7.1 Receiving an IFR with the BDLC module ...............................................................................................20-44
20.8.7.2 Receiving IFR Exceptions ........................................................................................................................20-45
20.8.8 Special BDLC Module Operations ................................................................................................................20-45