Freescale Semiconductor MPC5200B - Manual (Page 333)

MPC5200B Users Guide, Rev. 1
10-36 Freescale Semiconductor
Registers
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb
R Reserved FB R Max_Beats Reserved W Reserved DI
W
RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
0:3 Reserved Unused. Software should write zero to these bits.
4:7 PCI_cmd The user writes this field with the desired PCI command to present during the address
phase of each PCI transaction. The default is Memory Read Multiple. This field is not
checked for consistency and if written to an illegal value, unpredictable results will occur. If
not using the default value, the user should write this register only once prior to any packet
Restart.
8:15 Max_Retries The user writes this field with the maximum number of retries to permit “per packet”. The
retry counter is reset when the packet completes normally or is terminated by a master
abort, target abort, or an abort due to exceeding the retry limit. A slow or malfunctioning
Target might issue infinite disconnects and therefore permanently tie up the PCI bus.
A finite (0x01 to 0xff) Max_Retries value will detect this condition and generate an interrupt.
Setting Max_Retries to 0x00 will not generate any interrupt.
16:18 Reserved Unused. Software should write zero to these bits.
19 Full Burst
(FB)
This is the Full Burst bit. If Full Burst is set, no check of the Receive Fifo emptiness is done
and the PCI transaction is immediately started when Packet_Size register is written (and
SCPCI RX gains the PCI bus).
The PCI transaction will continue with multiple data beats UNTIL THE FULL PACKET IS
TRANSFERRED (up to 4G bytes). The Full Burst operation avoids latency time-out and will
not relinquish the bus until all Packet Bytes are received.
Note: All FIFO checks (by scpci Rx) are disabled in this mode. It is up to the Multi-Channel
DMA to keep the Rx FIFO from being overrun by the continuous incoming PCI burst data.
Note: It is recommended to use the Full Burst mode only for transactions where more than
32 Bytes should be received.
Note: Max_Beats must be set to 0.
20 Reserved Unused. Software should write zero to this bit.
21:23 Max_Beats The user writes this register with the desired number of PCI data beats to attempt on each
PCI transaction. The default setting of 0 represents the maximum of eight beats per
transaction. The receive controller will wait until sufficient space is in the Receive FIFO to
support the indicated number of beats (Note: Each beat is four bytes). In the case that a
packet is nearly complete and less than the Max_Beats number of bytes remain to complete
the packet, the Receive Controller will issue single-beat transactions automatically until the
packet is finished.
24:26 Reserved Unused. Software should write zero to these bits.
27 Word Transfer
(W)
The user writes this register to disable the two high byte enables of the PCI bus during
initiated read transactions. The default setting is 0, enable all 4 byte enables.
28:30 Reserved Unused. Software should write zero to these bits.
31 Disable
address
Incrementing
(DI)
The user writes this register to disable PCI address incrementing between transactions. The
default setting is 0, increment address by 4 (4 byte data bus).
Note: This feature is recommended when reading from an external FIFO (having a fixed
address).