Document Outline

• MPC5200B Users Guide
• Chapter 1 Introduction
  • 1.1 Overview
    • 1.1.1 Features
  • 1.2 Architecture
    • 1.2.1 Embedded e300 Core
    • 1.2.2 BestComm I / O Subsystem
      • 1.2.2.1 Programmable Serial Controllers ( PSCs )
      • 1.2.2.2 10 / 100 Ethernet Controller
      • 1.2.2.3 Universal Serial Bus ( USB )
      • 1.2.2.4 Infrared Support
      • 1.2.2.5 Inter-Integrated Circuit ( I 2 C )
      • 1.2.2.6 Serial Peripheral Interface ( SPI )
    • 1.2.3 Controller Area Network ( CAN )
    • 1.2.4 Byte Data Link Controller - Digital BDLC-D
    • 1.2.5 System Level Interfaces
      • 1.2.5.1 Chip Selects
      • 1.2.5.2 Interrupt Controller
      • 1.2.5.3 Timers
      • 1.2.5.4 General Purpose Input / Outputs ( GPIO )
      • 1.2.5.5 Functional Pin Multiplexing
      • 1.2.5.6 Real-Time Clock ( RTC )
    • 1.2.6 SDRAM Controller and Interface
    • 1.2.7 Multi-Function External LocalPlus Bus
    • 1.2.8 Power Management
    • 1.2.9 Systems Debug and Test
    • 1.2.10 Physical Characteristics
• Chapter 2 Signal Descriptions
  • 2.1 Overview
  • 2.2 Pinout Tables
• Chapter 3 Memory Map
  • 3.1 Overview
  • 3.2 Internal Register Memory Map
  • 3.3 MPC5200B Memory Map
    • 3.3.1 MPC5200B Internal Register Space
    • 3.3.2 External Busses
      • 3.3.2.1 SDRAM Bus
      • 3.3.2.2 LocalPlus Bus
    • 3.3.3 Memory Map Space Register Description
      • 3.3.3.1 Memory Address Base Register -MBAR + 0x0000
      • 3.3.3.2 Boot and Chip Select Addresses
      • 3.3.3.3 SDRAM Chip Select Configuration Registers
      • 3.3.3.4 IPBI Control Register and Wait State Enable -MBAR+0x0054
• Chapter 4 Resets and Reset Configuration
  • 4.1 Overview
  • 4.2 Hard and Soft Reset Pins
    • 4.2.1 Power-On Reset-PORRESET
    • 4.2.2 Hard Reset-HRESET
    • 4.2.3 Soft Reset-SRESET
  • 4.3 Reset Sequence
  • 4.4 Reset Operation
  • 4.5 Other Resets
  • 4.6 Reset Configuration
• Chapter 5 Clocks and Power Management
  • 5.1 Overview
  • 5.2 Clock Distribution Module (CDM)
  • 5.3 MPC5200B Clock Domains
    • 5.3.1 MPC5200B Top Level Clock Relations
    • 5.3.2 e300 Core Clock Domain
    • 5.3.3 Processor Bus (XLB ) Clock Domain
    • 5.3.4 SDRAM Memory Controller Clock Domain
    • 5.3.5 IPB Clock Domain
    • 5.3.6 PCI Clock Domain
  • 5.4 Power Management
    • 5.4.1 Full-Power Mode
    • 5.4.2 Power Conservation Modes
    • 5.4.3 e300 Core Power Modes
      • 5.4.3.1 Dynamic Power Mode
      • 5.4.3.2 Doze Mode
      • 5.4.3.3 Nap Mode
      • 5.4.3.4 Sleep Mode
    • 5.4.4 Deep-Sleep Mode
      • 5.4.4.1 Entering Deep Sleep
      • 5.4.4.2 Exiting Deep Sleep
  • 5.5 CDM Registers
    • 5.5.1 CDM JTAG ID Number Register-MBAR + 0x0200
    • 5.5.2 CDM Power On Reset Configuration Register-MBAR + 0x0204
    • 5.5.3 CDM Bread Crumb Register-MBAR + 0x0208
    • 5.5.4 CDM Configuration Register-MBAR + 0x020C
    • 5.5.5 CDM 48MHz Fractional Divider Configuration Register-MBAR + 0x0210
    • 5.5.6 CDM Clock Enable Register-MBAR + 0x0214
    • 5.5.7 CDM System Oscillator Configuration Register-MBAR + 0x0218
    • 5.5.8 CDM Clock Control Sequencer Configuration Register-MBAR + 0x021C
    • 5.5.9 CDM Soft Reset Register-MBAR + 0x0220
    • 5.5.10 CDM System PLL Status Register-MBAR + 0x0224
    • 5.5.11 PSC1 Mclock Config Register-MBAR + 0x0228
    • 5.5.12 PSC2 Mclock Config Register-MBAR + 0x022C
    • 5.5.13 PSC3 Mclock Config Register-MBAR + 0x0230
    • 5.5.14 PSC6 (IrDA) Mclock Config Register-MBAR + 0x0234
• Chapter 6 e300 Processor Core
  • 6.1 Overview
  • 6.2 MPC5200B e300 Processor Core Functional Overview
  • 6.3 e300 Core Reference Manual
  • 6.4 Not supported e300 Core Features
    • 6.4.1 Not supported instruction
    • 6.4.2 Not supported XLB parity feature
• Chapter 7 System Integration Unit ( SIU )
  • 7.1 Overview
  • 7.2 Interrupt Controller
    • 7.2.1 Block Description
      • 7.2.1.1 Machine Check Pin-core_mcp
      • 7.2.1.2 System Management Interrupt-core_smi
      • 7.2.1.3 Standard Interrupt-core_int
    • 7.2.2 Interface Description
    • 7.2.3 Programming Note
    • 7.2.4 Interrupt Controller Registers
      • 7.2.4.1 ICTL Peripheral Interrupt Mask Register-MBAR + 0x0500
      • 7.2.4.2 ICTL Peripheral Priority and HI / LO Select 1 Register -MBAR + 0x0504
      • 7.2.4.3 ICTL Peripheral Priority and HI / LO Select 2 Register -MBAR + 0x0508
      • 7.2.4.4 ICTL Peripheral Priority and HI / LO Select 3 Register -MBAR + 0x050C
      • 7.2.4.5 ICTL External Enable and External Types Register -MBAR + 0x0510
      • 7.2.4.6 ICTL Critical Priority and Main Interrupt Mask Register-MBAR + 0x0514
      • 7.2.4.7 ICTL Main Interrupt Priority and INT / SMI Select 1 Register -MBAR + 0x0518
      • 7.2.4.8 ICTL Main Interrupt Priority and INT / SMI Select 2 Register-MBAR + 0x051C
      • 7.2.4.9 ICTL Perstat, MainStat, MainStat, CritStat Encoded Register-MBAR + 0x0524
      • 7.2.4.10 ICTL Critical Interrupt Status All Register-MBAR + 0x0528
      • 7.2.4.11 ICTL Main Interrupt Status All Register-MBAR + 0x052C
      • 7.2.4.12 ICTL Peripheral Interrupt Status All Register-MBAR + 0x0530
      • 7.2.4.13 ICTL Peripheral Interrupt Status All Register-MBAR + 0x0538
      • 7.2.4.14 ICTL Main Interrupt Emulation All Register-MBAR + 0x0540
      • 7.2.4.15 ICTL Peripheral Interrupt Emulation All Register-MBAR + 0x0544
      • 7.2.4.16 ICTL IRQ Interrupt Emulation All Register-MBAR + 0x0548
  • 7.3 General Purpose I / O ( GPIO )
    • 7.3.1 GPIO Pin Multiplexing
      • 7.3.1.1 PSC1 ( UART1 / AC97 / CODEC1 )
      • 7.3.1.2 PSC2 ( CAN1/2/UART2 / AC97 / CODEC2 )
      • 7.3.1.3 PSC3 ( USB2 / CODEC3 / SPI / UART3 )
      • 7.3.1.4 USB1/ RST_CONFIG
      • 7.3.1.5 Ethernet / USB2 /UART4/5/J1850/ RST_CONFIG
      • 7.3.1.6 PSC6
      • 7.3.1.7 I2C
      • 7.3.1.8 GPIO Timer Pins
      • 7.3.1.9 Dedicated GPIO Port
    • 7.3.2 GPIO Programmer’s Model
      • 7.3.2.1 GPIO Standard Registers-MBAR + 0x0B00
        • 7.3.2.1.1 GPS Port Configuration Register-MBAR + 0x0B00
        • 7.3.2.1.2 GPS Simple GPIO Enables Register-MBAR + 0x0B04
        • 7.3.2.1.3 GPS Simple GPIO Open Drain Type Register -MBAR + 0x0B08
        • 7.3.2.1.4 GPS Simple GPIO Data Direction Register-MBAR + 0x0B0C
        • 7.3.2.1.5 GPS Simple GPIO Data Output Values Register -MBAR + 0x0B10
        • 7.3.2.1.6 GPS Simple GPIO Data Input Values Register -MBAR + 0x0B14
        • 7.3.2.1.7 GPS GPIO Output-Only Enables Register -MBAR + 0x0B18
        • 7.3.2.1.8 GPS GPIO Output-Only Data Value Out Register -MBAR + 0x0B1C
        • 7.3.2.1.9 GPS GPIO Simple Interrupt Enable Register-MBAR + 0x0B20
        • 7.3.2.1.10 GPS GPIO Simple Interrupt Open-Drain Emulation Register -MBAR + 0x0B24
        • 7.3.2.1.11 GPS GPIO Simple Interrupt Data Direction Register -MBAR + 0x0B28
        • 7.3.2.1.12 GPS GPIO Simple Interrupt Data Value Out Register -MBAR + 0x0B2C
        • 7.3.2.1.13 GPS GPIO Simple Interrupt Interrupt Enable Register -MBAR + 0x0B30
        • 7.3.2.1.14 GPS GPIO Simple Interrupt Interrupt Types Register -MBAR + 0x0B34
        • 7.3.2.1.15 GPS GPIO Simple Interrupt Master Enable Register -MBAR + 0x0B38
        • 7.3.2.1.16 GPS GPIO Simple Interrupt Status Register-MBAR + 0x0B3C
      • 7.3.2.2 WakeUp GPIO Registers-MBAR + 0x0C00
        • 7.3.2.2.1 GPW WakeUp GPIO Enables Register-MBAR + 0x0C00
        • 7.3.2.2.2 GPW WakeUp GPIO Open Drain Emulation Register -MBAR + 0x0C04
        • 7.3.2.2.3 GPW WakeUp GPIO Data Direction Register-MBAR + 0x0C08
        • 7.3.2.2.4 GPW WakeUp GPIO Data Value Out Register -MBAR + 0x0C0C
        • 7.3.2.2.5 GPW WakeUp GPIO Interrupt Enable Register-MBAR + 0x0C10
        • 7.3.2.2.6 GPW WakeUp GPIO Individual Interrupt Enable Register -MBAR + 0x0C14
        • 7.3.2.2.7 GPW WakeUp GPIO Interrupt Types Register-MBAR + 0x0C18
        • 7.3.2.2.8 GPW WakeUp GPIO Master Enables Register -MBAR + 0x0C1C
        • 7.3.2.2.9 GPW WakeUp GPIO Data Input Values Register -MBAR + 0x0C20
        • 7.3.2.2.10 GPW WakeUp GPIO Status Register-MBAR + 0x0C24
  • 7.4 General Purpose Timers ( GPT )
    • 7.4.1 Timer Configuration Method
    • 7.4.2 Mode Overview
    • 7.4.3 Programming Notes
    • 7.4.4 GPT Registers-MBAR + 0x0600
      • 7.4.4.1 GPT 0 Enable and Mode Select Register-MBAR + 0x0600
      • 7.4.4.2 GPT 0 Counter Input Register-MBAR + 0x0604
      • 7.4.4.3 GPT 0 PWM Configuration Register-MBAR + 0x0608
      • 7.4.4.4 GPT 0 Status Register-MBAR + 0x060C
  • 7.5 Slice Timers
    • 7.5.1 SLT Registers-MBAR + 0x0700
      • 7.5.1.1 SLT 0 Terminal Count Register-MBAR + 0x0700
      • 7.5.1.2 SLT 0 Control Register-MBAR + 0x0704
      • 7.5.1.3 SLT 0 Count Value Register-MBAR + 0x0708
      • 7.5.1.4 SLT 0 Timer Status Register-MBAR + 0x070C
  • 7.6 Real-Time Clock
    • 7.6.1 Real-Time Clock Signals
    • 7.6.2 Programming Note
    • 7.6.3 RTC Interface Registers-MBAR + 0x0800
      • 7.6.3.1 RTC Time Set Register-MBAR + 0x0800
      • 7.6.3.2 RTC Date Set Register-MBAR + 0x0804
      • 7.6.3.3 RTC New Year and Stopwatch Register-MBAR + 0x0808
      • 7.6.3.4 RTC Alarm and Interrupt Enable Register-MBAR + 0x080C
      • 7.6.3.5 RTC Current Time Register-MBAR + 0x0810
      • 7.6.3.6 RTC Current Date Register-MBAR + 0x0814
      • 7.6.3.7 RTC Alarm and Stopwatch Interrupt Register-MBAR + 0x0818
      • 7.6.3.8 RTC Periodic Interrupt and Bus Error Register-MBAR + 0x081C
      • 7.6.3.9 RTC Test Register/Divides Register-MBAR + 0x0820
• Chapter 8 SDRAM Memory Controller
  • 8.1 Overview
  • 8.2 Terminology and Notation
    • 8.2.1 “Endian”-ness
  • 8.3 Features
    • 8.3.1 Devices Supported
  • 8.4 Functional Description
    • 8.4.1 External Signals (SDRAM Side)
    • 8.4.2 Block Diagram
    • 8.4.3 Transfer Size
    • 8.4.4 Commands
      • 8.4.4.1 Load Mode/Extended Mode Register Command
      • 8.4.4.2 Precharge All Banks Command
      • 8.4.4.3 Row and Bank Active Command
      • 8.4.4.4 Read Command
      • 8.4.4.5 Write Command
      • 8.4.4.6 Burst Terminate Command
      • 8.4.4.7 Auto Refresh Command
      • 8.4.4.8 Self Refresh and Power Down Commands
  • 8.5 Operation
    • 8.5.1 Power-Up Initialization
    • 8.5.2 Read Clock
  • 8.6 Programming the SDRAM Controller
  • 8.7 Memory Controller Registers (MBAR+0x0100:0x010C)
    • 8.7.1 Mode Register-MBAR + 0x0100
    • 8.7.2 Control Register-MBAR + 0x0104
    • 8.7.3 Configuration Register 1-MBAR + 0x0108
    • 8.7.4 Configuration Register 2-MBAR + 0x010C
  • 8.8 Address Bus Mapping
    • 8.8.1 Example-Physical Address Multiplexing
• Chapter 9 LocalPlus Bus (External Bus Interface)
  • 9.1 Overview
  • 9.2 Features
  • 9.3 Interface
    • 9.3.1 External Signals
    • 9.3.2 Block Diagram
  • 9.4 Modes of Operation
    • 9.4.1 Non-MUXed Mode
    • 9.4.2 MUXed Mode
      • 9.4.2.1 Address Tenure
      • 9.4.2.2 Data Tenure
  • 9.5 Configuration
    • 9.5.1 Boot Configuration
    • 9.5.2 Chip Selects Configuration
    • 9.5.3 Reset Configuration
  • 9.6 DMA (BestComm) Interface (SCLPC)
  • 9.7 Programmer’s Model
    • 9.7.1 Chip Select / LPC Registers-MBAR + 0x0300
      • 9.7.1.1 Chip Select 0/Boot Configuration Register-MBAR + 0x0300
      • 9.7.1.2 Chip Select 1 Configuration Register-MBAR + 0x0304
      • 9.7.1.3 Chip Select Control Register-MBAR + 0x0318
      • 9.7.1.4 Chip Select Status Register-MBAR + 0x031C
      • 9.7.1.5 Chip Select Burst Control Register-MBAR + 0x0328
      • 9.7.1.6 Chip Select Deadcycle Control Register-MBAR + 0x032C
    • 9.7.2 SCLPC Registers-MBAR + 0x3C00
      • 9.7.2.1 SCLPC Packet Size Register-MBAR + 0x3C00
      • 9.7.2.2 SCLPC Start Address Register-MBAR + 0x3C04
      • 9.7.2.3 SCLPC Control Register-MBAR + 0x3C08
      • 9.7.2.4 SCLPC Enable Register-MBAR + 0x3C0C
      • 9.7.2.5 SCLPC Bytes Done Status Register-MBAR + 0x3C14
    • 9.7.3 SCLPC FIFO Registers-MBAR + 0x3C40
      • 9.7.3.1 LPC Rx / Tx FIFO Data Word Register-MBAR + 0x3C40
      • 9.7.3.2 LPC Rx / Tx FIFO Status Register-MBAR + 0x3C44
      • 9.7.3.3 LPC Rx / Tx FIFO Control Register-MBAR + 0x3C48
      • 9.7.3.4 LPC Rx / Tx FIFO Alarm Register-MBAR + 0x3C4C
      • 9.7.3.5 LPC Rx / Tx FIFO Read Pointer Register-MBAR + 0x3C50
      • 9.7.3.6 LPC Rx / Tx FIFO Write Pointer Register-MBAR + 0x3C54
• Chapter 10 PCI Controller
  • 10.1 Overview
    • 10.1.1 Features
    • 10.1.2 Block Diagram
  • 10.2 PCI External Signals
    • 10.2.1 PCI_AD[31:0] - Address/Data Bus
    • 10.2.2 PCI_CBE[3:0] - Command/Byte Enables
    • 10.2.3 PCI_DEVSEL - Device Select
    • 10.2.4 PCI_FRAME - Frame
    • 10.2.5 PCI_IDSEL - Initialization Device Select
    • 10.2.6 PCI_IRDY - Initiator Ready
      • 10.2.6.1 PCI_PAR - Parity
    • 10.2.7 PCI_CLK - PCI Clock
    • 10.2.8 PCI_PERR - Parity Error
    • 10.2.9 PCI_RST - Reset
    • 10.2.10 PCI_SERR - System Error
    • 10.2.11 PCI_STOP - Stop
    • 10.2.12 PCI_TRDY - Target Ready
  • 10.3 Registers
    • 10.3.1 PCI Controller Type 0 Configuration Space
      • 10.3.1.1 Device ID/ Vendor ID Registers PCIIDR(R) -MBAR + 0x0D00
      • 10.3.1.2 Status/Command Registers PCISCR(R/RW/RWC) -MBAR + 0x0D04
      • 10.3.1.3 Revision ID/ Class Code Registers PCICCRIR(R) -MBAR + 0x0D08
      • 10.3.1.4 Configuration 1 Register PCICR1(R/RW) -MBAR + 0x0D0C
      • 10.3.1.5 Base Address Register 0 PCIBAR0(RW) -MBAR + 0x0D10
      • 10.3.1.6 Base Address Register 1 PCIBAR1(RW) -MBAR + 0x0D14
      • 10.3.1.7 CardBus CIS Pointer Register PCICCPR(RW) -MBAR + 0x0D28
      • 10.3.1.8 Subsystem ID/ Subsystem Vendor ID Registers PCISID(R)-MBAR + 0x0D2C
      • 10.3.1.9 Expansion ROM Base Address PCIERBAR(R) -MBAR + 0x0D30
      • 10.3.1.10 Capabilities Pointer (Cap_Ptr) PCICPR(R)-MBAR + 0x0D34
      • 10.3.1.11 Configuration 2 Register PCICR2 (R/RW) -MBAR + 0x0D3C
    • 10.3.2 General Control/Status Registers
      • 10.3.2.1 Global Status/Control Register PCIGSCR(RW) -MBAR + 0x0D60
      • 10.3.2.2 Target Base Address Translation Register 0 PCITBATR0(RW) -MBAR + 0x0D64
      • 10.3.2.3 Target Base Address Translation Register 1 PCITBATR1(RW) -MBAR + 0x0D68
      • 10.3.2.4 Target Control Register PCITCR(RW) -MBAR + 0x0D6C
      • 10.3.2.5 Initiator Window 0 Base/Translation Address Register PCIIW0BTAR(RW)-MBAR + 0x0D70
      • 10.3.2.6 Initiator Window 1 Base/Translation Address Register PCIIW1BTAR(RW) -MBAR + 0x0D74
      • 10.3.2.7 Initiator Window 2 Base/Translation Address Register PCIIW2BTAR(RW) -MBAR + 0x0D78
      • 10.3.2.8 Initiator Window Configuration Register PCIIWCR(RW) -MBAR + 0x0D80
      • 10.3.2.9 Initiator Control Register PCIICR(RW) -MBAR + 0x0D84
      • 10.3.2.10 Initiator Status Register PCIISR(RWC) -MBAR + 0x0D88
      • 10.3.2.11 PCI Arbiter Register PCIARB(RW) -MBAR + 0x0D8C
      • 10.3.2.12 Configuration Address Register PCICAR (RW) -MBAR + 0x0DF8
    • 10.3.3 Communication Sub-System Interface Registers
      • 10.3.3.1 Multi-Channel DMA Transmit Interface
        • 10.3.3.1.1 Tx Packet Size PCITPSR(RW) -MBAR + 0x3800
        • 10.3.3.1.2 Tx Start Address PCITSAR(RW) -MBAR + 0x3804
        • 10.3.3.1.3 Tx Transaction Control Register PCITTCR(RW) -MBAR + 0x3808
        • 10.3.3.1.4 Tx Enables PCITER(RW)-MBAR + 0x380C
        • 10.3.3.1.5 Tx Next Address PCITNAR(R) -MBAR + 0x3810
        • 10.3.3.1.6 Tx Last Word PCITLWR(R) -MBAR + 0x3814
        • 10.3.3.1.7 Tx Bytes Done Counts PCITDCR(R) -MBAR + 0x3818
        • 10.3.3.1.8 Tx Packets Done Counts PCITPDCR(R) -MBAR + 0x3820
        • 10.3.3.1.9 Tx Status PCITSR(RWC) -MBAR + 0x381C
        • 10.3.3.1.10 Tx FIFO Data Register PCITFDR(RW) -MBAR + 0x3840
        • 10.3.3.1.11 Tx FIFO Status Register PCITFSR(R/RWC) -MBAR + 0x3844
        • 10.3.3.1.12 Tx FIFO Control Register PCITFCR(RW) -MBAR + 0x3848
        • 10.3.3.1.13 Tx FIFO Alarm Register PCITFAR(RW) -MBAR + 0x384C
        • 10.3.3.1.14 Tx FIFO Read Pointer Register PCITFRPR(RW) -MBAR + 0x3850
        • 10.3.3.1.15 Tx FIFO Write Pointer Register PCITFWPR(RW) -MBAR + 0x3854
      • 10.3.3.2 Multi-Channel DMA Receive Interface
        • 10.3.3.2.1 Rx Packet Size PCIRPSR(RW) -MBAR + 0x3880
        • 10.3.3.2.2 Rx Start Address PCIRSAR (RW) -MBAR + 0x3884
        • 10.3.3.2.3 Rx Transaction Control Register PCIRTCR(RW) -MBAR + 0x3888
        • 10.3.3.2.4 Rx Enables PCIRER (RW) -MBAR + 0x388C
        • 10.3.3.2.5 Rx Next Address PCIRNAR(R) -MBAR + 0x3890
        • 10.3.3.2.6 Rx Last Word PCIRLWR(R) -MBAR + 0x3894
        • 10.3.3.2.7 Rx Bytes Done Counts PCIRDCR(R) -MBAR + 0x3898
        • 10.3.3.2.8 Rx Packets Done Counts PCIRPDCR(R) -MBAR + 0x38A0
        • 10.3.3.2.9 Rx Status PCIRSR (R/sw1) -MBAR + 0x389C
        • 10.3.3.2.10 Rx FIFO Data Register PCIRFDR(RW) -MBAR + 0x38C0
        • 10.3.3.2.11 Rx FIFO Status Register PCIRFSR(R/sw1) -MBAR + 0x38C4
        • 10.3.3.2.12 Rx FIFO Control Register PCIRFCR(RW) -MBAR + 0x38C8
        • 10.3.3.2.13 Rx FIFO Alarm Register PCIRFAR(RW) -MBAR + 0x38CC
        • 10.3.3.2.14 Rx FIFO Read Pointer Register PCIRFRPR(RW) -MBAR + 0x38D0
        • 10.3.3.2.15 Rx FIFO Write Pointer Register PCIRFWPR (RW) -MBAR + 0x38D4
  • 10.4 Functional Description
    • 10.4.1 PCI Bus Protocol
      • 10.4.1.1 PCI Bus Background
      • 10.4.1.2 Basic Transfer Control
      • 10.4.1.3 PCI Transactions
      • 10.4.1.4 PCI Bus Commands
      • 10.4.1.5 Addressing
        • 10.4.1.5.1 Memory space addressing
        • 10.4.1.5.2 I/O space addressing
        • 10.4.1.5.3 Configuration space addressing and transactions
        • 10.4.1.5.4 Address decoding
    • 10.4.2 Initiator Arbitration
      • 10.4.2.1 Priority Scheme
    • 10.4.3 Configuration Interface
    • 10.4.4 XL bus Initiator Interface
      • 10.4.4.1 Endian Translation
      • 10.4.4.2 Configuration Mechanism
        • 10.4.4.2.1 Type 0 Configuration Translation
        • 10.4.4.2.2 Type 1 Configuration Translation
        • 10.4.4.2.3 Interrupt Acknowledge Transactions
        • 10.4.4.2.4 Special Cycle Transactions
      • 10.4.4.3 Transaction Termination
    • 10.4.5 XL bus Target Interface
      • 10.4.5.1 Reads from Local Memory
      • 10.4.5.2 Local Memory Writes
      • 10.4.5.3 Data Translation
      • 10.4.5.4 Target Abort
      • 10.4.5.5 Latrule Disable
    • 10.4.6 Communication Sub-System Initiator Interface
      • 10.4.6.1 Access Width
      • 10.4.6.2 Addressing
      • 10.4.6.3 Data Translation
      • 10.4.6.4 Initialization
      • 10.4.6.5 Restart and Reset
      • 10.4.6.6 PCI Commands
      • 10.4.6.7 FIFO Considerations
      • 10.4.6.8 Alarms
      • 10.4.6.9 Bus Errors
    • 10.4.7 PCI - Supported Clock Ratios
    • 10.4.8 Interrupts
      • 10.4.8.1 PCI Bus Interrupts
      • 10.4.8.2 Internal Interrupt
  • 10.5 PCI Arbiter
  • 10.6 Application Information
    • 10.6.1 XL bus Initiated Transaction Mapping
    • 10.6.2 Address Maps
      • 10.6.2.1 Address Translation
        • 10.6.2.1.1 Inbound Address Translation
        • 10.6.2.1.2 Outbound Address Translation
        • 10.6.2.1.3 Base Address Register Overview
    • 10.6.3 XL bus Arbitration Priority
• Chapter 11 ATA Controller
  • 11.1 Overview
  • 11.2 BestComm Key Features
    • 11.2.1 BestComm Read
    • 11.2.2 BestComm Write
  • 11.3 ATA Register Interface
    • 11.3.1 ATA Host Registers-MBAR + 0x3A00
      • 11.3.1.1 ATA Host Configuration Register-MBAR + 0x3A00
      • 11.3.1.2 ATA Host Status Register-MBAR + 0x3A04
      • 11.3.1.3 ATA PIO Timing 1 Register-MBAR + 0x3A08
      • 11.3.1.4 ATA PIO Timing 2 Register-MBAR + 0x3A0C
      • 11.3.1.5 ATA Multiword DMA Timing 1 Register-MBAR + 0x3A10
      • 11.3.1.6 ATA Multiword DMA Timing 2 Register-MBAR + 0x3A14
      • 11.3.1.7 ATA Ultra DMA Timing 1 Register-MBAR + 0x3A18
      • 11.3.1.8 ATA Ultra DMA Timing 2 Register-MBAR + 0x3A1C
      • 11.3.1.9 ATA Ultra DMA Timing 3 Register-MBAR + 0x 3A20
      • 11.3.1.10 ATA Ultra DMA Timing 4 Register-MBAR + 0x3A24
      • 11.3.1.11 ATA Ultra DMA Timing 5 Register-MBAR + 0x3A28
      • 11.3.1.12 ATA Share Count Register-MBAR + 0x3A2C
    • 11.3.2 ATA FIFO Registers-MBAR + 0x3A00
      • 11.3.2.1 ATA Rx / Tx FIFO Data Word Register-MBAR + 0x3A3C
      • 11.3.2.2 ATA Rx / Tx FIFO Status Register-MBAR + 0x3A40
      • 11.3.2.3 ATA Rx / Tx FIFO Control Register-MBAR + 0x3A44
      • 11.3.2.4 ATA Rx / Tx FIFO Alarm Register-MBAR + 0x3A48
      • 11.3.2.5 ATA Rx / Tx FIFO Read Pointer Register-MBAR + 0x3A4C
      • 11.3.2.6 ATA Rx / Tx FIFO Write Pointer Register-MBAR + 0x3A50
    • 11.3.3 ATA Drive Registers-MBAR + 0x3A00
      • 11.3.3.1 ATA Drive Device Control Register-MBAR + 0x3A5C
      • 11.3.3.2 ATA Drive Alternate Status Register-MBAR + 0x3A5C
      • 11.3.3.3 ATA Drive Data Register-MBAR + 0x3A60
      • 11.3.3.4 ATA Drive Features Register-MBAR + 0x3A64
      • 11.3.3.5 ATA Drive Error Register-MBAR + 0x3A64
      • 11.3.3.6 ATA Drive Sector Count Register-MBAR + 0x3A68
      • 11.3.3.7 ATA Drive Sector Number Register-MBAR + 0x3A6C
      • 11.3.3.8 ATA Drive Cylinder Low Register-MBAR + 0x3A70
      • 11.3.3.9 ATA Drive Cylinder High Register-MBAR + 0x3A74
      • 11.3.3.10 ATA Drive Device / Head Register-MBAR + 0x3A78
      • 11.3.3.11 ATA Drive Device Command Register-MBAR + 0x3A7C
      • 11.3.3.12 ATA Drive Device Status Register-MBAR + 0x3A7C
  • 11.4 ATA Host Controller Operation
    • 11.4.1 PIO State Machine
    • 11.4.2 DMA State Machine
      • 11.4.2.1 Software Requirements
  • 11.5 Signals and Connections
  • 11.6 ATA Interface Description
  • 11.7 ATA Bus Background
    • 11.7.1 Terminology
    • 11.7.2 ATA Modes
    • 11.7.3 ATA Addressing
      • 11.7.3.1 ATA Register Addressing
      • 11.7.3.2 Drive Interrupt
      • 11.7.3.3 Sector Addressing
      • 11.7.3.4 Physical / Logical Addressing Modes
    • 11.7.4 ATA Transactions
      • 11.7.4.1 PIO Mode Transactions
        • 11.7.4.1.1 Class 1-PIO Read
        • 11.7.4.1.2 Class 2-PIO Write
        • 11.7.4.1.3 Class 3-Non-Data Command
      • 11.7.4.2 DMA Protocol
      • 11.7.4.3 Multiword DMA Transactions
        • 11.7.4.3.1 Class 4-DMA Command
      • 11.7.4.4 Ultra DMA Protocol
  • 11.8 ATA RESET / Power-Up
    • 11.8.1 Hardware Reset
    • 11.8.2 Software Reset
  • 11.9 ATA I/O Cable Specifications
• Chapter 12 Universal Serial Bus ( USB )
  • 12.1 Overview
  • 12.2 Data Transfer Types
  • 12.3 Host Controller Interface
    • 12.3.1 Communication Channels
    • 12.3.2 Data Structures
  • 12.4 Host Control ( HC ) Operational Registers
    • 12.4.1 Programming Note
    • 12.4.2 Control and Status Partition-MBAR + 0x1000
      • 12.4.2.1 USB HC Revision Register-MBAR + 0x1000
      • 12.4.2.2 USB HC Control Register-MBAR + 0x1004
      • 12.4.2.3 USB HC Command Status Register-MBAR + 0x1008
      • 12.4.2.4 USB HC Interrupt Status Register -MBAR + 0x 100C
      • 12.4.2.5 USB HC Interrupt Enable Register-MBAR + 0x 1010
      • 12.4.2.6 USB HC Interrupt Disable Register-MBAR + 0x 1014
    • 12.4.3 Memory Pointer Partition-MBAR + 0x1018
      • 12.4.3.1 USB HC HCCA Register-MBAR + 0x1018
      • 12.4.3.2 USB HC Period Current Endpoint Descriptor Register -MBAR + 0x101C
      • 12.4.3.3 USB HC Control Head Endpoint Descriptor Register -MBAR + 0x1020
      • 12.4.3.4 USB HC Control Current Endpoint Descriptor Register -MBAR + 0x1024
      • 12.4.3.5 USB HC Bulk Head Endpoint Descriptor Register-MBAR + 0x1028
      • 12.4.3.6 USB HC Bulk Current Endpoint Descriptor Register-MBAR + 0x102C
      • 12.4.3.7 USB HC Done Head Register-MBAR + 0x1030
    • 12.4.4 Frame Counter Partition-MBAR + 0x1034
      • 12.4.4.1 USB HC Frame Interval Register-MBAR + 0x1034
      • 12.4.4.2 USB HC Frame Remaining Register-MBAR + 0x1038
      • 12.4.4.3 USB HC Frame Number Register-MBAR + 0x103C
      • 12.4.4.4 USB HC Periodic Start Register-MBAR + 0x1040
      • 12.4.4.5 USB HC LS Threshold Register-MBAR + 0x1044
    • 12.4.5 Root Hub Partition-MBAR + 0x1048
      • 12.4.5.1 USB HC Rh Descriptor A Register-MBAR + 0x1048
      • 12.4.5.2 USB HC Rh Descriptor B Register-MBAR + 0x104C
      • 12.4.5.3 USB HC Rh Status Register-MBAR + 0x1050
      • 12.4.5.4 USB HC Rh Port1 Status Register-MBAR + 0x1054
      • 12.4.5.5 USB HC Rh Port2 Status Register-MBAR + 0x1058
• Chapter 13 BestComm
  • 13.1 Overview
  • 13.2 BestComm Functional Description
  • 13.3 Features summary
  • 13.4 Descriptors
  • 13.5 Tasks
  • 13.6 Memory Map/ Register Definitions
  • 13.7 Task Table (Entry Table)
  • 13.8 Task Descriptor Table
  • 13.9 Variable Table
  • 13.10 Function Descriptor Table
  • 13.11 Context Save Area
  • 13.12 External DMA Request
  • 13.13 External DMA Breakpoint
  • 13.14 BestComm XLB Address Snooping
  • 13.15 BestComm DMA Registers-MBAR + 0x1200
    • 13.15.1 SDMA Task Bar Register-MBAR + 0x1200
    • 13.15.2 SDMA Current Pointer Register-MBAR + 0x1204
    • 13.15.3 SDMA End Pointer Register-MBAR + 0x1208
    • 13.15.4 SDMA Variable Pointer Register-MBAR + 0x120C
    • 13.15.5 SDMA Interrupt Vector, PTD Control Register-MBAR + 0x1210
    • 13.15.6 SDMA Interrupt Pending Register-MBAR + 0x1214
    • 13.15.7 SDMA Interrupt Mask Register-MBAR + 0x1218
    • 13.15.8 SDMA Task Control 0 Register-MBAR + 0x121C
    • 13.15.9 SDMA Task Control 2 Register-MBAR + 0x1220
    • 13.15.10 SDMA Task Control 4 Register-MBAR + 0x1224
    • 13.15.11 SDMA Task Control 6 Register-MBAR + 0x1228
    • 13.15.12 SDMA Task Control 8 Register-MBAR + 0x122C
    • 13.15.13 SDMA Task Control A Register-MBAR + 0x1230
    • 13.15.14 SDMA Task Control C Register-MBAR + 0x1234
    • 13.15.15 SDMA Task Control E Register-MBAR + 0x1238
    • 13.15.16 SDMA Initiator Priority 0 Register-MBAR + 0x123C
    • 13.15.17 SDMA Initiator Priority 4 Register-MBAR + 0x1240
    • 13.15.18 SDMA Initiator Priority 8 Register-MBAR + 0x1244
    • 13.15.19 SDMA Initiator Priority 12 Register-MBAR + 0x1248
    • 13.15.20 SDMA Initiator Priority 16 Register-MBAR + 0x124C
    • 13.15.21 SDMA Initiator Priority 20 Register-MBAR + 0x1250
    • 13.15.22 SDMA Initiator Priority 24 Register-MBAR + 0x1254
    • 13.15.23 SDMA Initiator Priority 28 Register-MBAR + 0x1258
    • 13.15.24 SDMA Requestor MuxControl-MBAR + 0x125C
    • 13.15.25 SDMA task Size0-MBAR + 0x1260
    • 13.15.26 SDMA task 0 & task Size 1 map
    • 13.15.27 SDMA Reserved Register 1-MBAR + 0x1268
    • 13.15.28 SDMA Reserved Register 2-MBAR + 0x126C
    • 13.15.29 SDMA Debug Module Comparator 1, Value 1 Register-MBAR + 0x1270
    • 13.15.30 SDMA Debug Module Comparator 2, Value 2 Register-MBAR + 0x1274
    • 13.15.31 SDMA Debug Module Control Register-MBAR + 0x1278
    • 13.15.32 SDMA Debug Module Status Register-MBAR + 0x127C
  • 13.16 On-Chip SRAM
  • 13.17 Programming Model
    • 13.17.1 Task Table
      • 13.17.1.1 Integer Mode
      • 13.17.1.2 Pack
    • 13.17.2 Variable Table
• Chapter 14 Fast Ethernet Controller ( FEC )
  • 14.1 Overview
    • 14.1.1 Features
  • 14.2 Modes of Operation
    • 14.2.1 Full- and Half-Duplex Operation
    • 14.2.2 10 Mbps and 100 Mbps MII Interface Operation
    • 14.2.3 10 Mbps 7-Wire Interface Operation
    • 14.2.4 Address Recognition Options
    • 14.2.5 Internal Loopback
  • 14.3 I / O Signal Overview
    • 14.3.1 Detailed Signal Descriptions
      • 14.3.1.1 MII Ethernet MAC-PHY Interface
      • 14.3.1.2 MII Management Frame Structure
        • 14.3.1.2.1 MII Management Register Set
  • 14.4 FEC Memory Map and Registers
    • 14.4.1 Control and Status (CSR) Memory Map
    • 14.4.2 MIB Block Counters Memory Map
  • 14.5 FEC Registers-MBAR + 0x3000
    • 14.5.1 FEC ID Register-MBAR + 0x3000
    • 14.5.2 FEC Interrupt Event Register-MBAR + 0x3004
    • 14.5.3 FEC Interrupt Enable Register-MBAR + 0x3008
    • 14.5.4 FEC Rx Descriptor Active Register-MBAR + 0x3010
    • 14.5.5 FEC Tx Descriptor Active Register-MBAR + 0x3014
    • 14.5.6 FEC Ethernet Control Register-MBAR + 0x3024
    • 14.5.7 FEC MII Management Frame Register-MBAR + 0x3040
    • 14.5.8 FEC MII Speed Control Register-MBAR + 0x3044
    • 14.5.9 FEC MIB Control Register-MBAR + 0x3064
    • 14.5.10 FEC Receive Control Register-MBAR + 0x3084
    • 14.5.11 FEC Hash Register-MBAR + 0x3088
    • 14.5.12 FEC Tx Control Register-MBAR + 0x30C4
    • 14.5.13 FEC Physical Address Low Register-MBAR + 0x30E4
    • 14.5.14 FEC Physical Address High Register-MBAR + 0x30E8
    • 14.5.15 FEC Opcode / Pause Duration Register-MBAR + 0x30EC
    • 14.5.16 FEC Descriptor Individual Address 1 Registe-MBAR + 0x3118
    • 14.5.17 FEC Descriptor Individual Address 2 Register-MBAR + 0x311C
    • 14.5.18 FEC Descriptor Group Address 1 Register-MBAR + 0x3120
    • 14.5.19 FEC Descriptor Group Address 2 Register-MBAR + 0x3124
    • 14.5.20 FEC Tx FIFO Watermark Register-MBAR + 0x3144
  • 14.6 FIFO Interface
    • 14.6.1 FEC Rx FIFO Data Register-MBAR + 0x3184
  • 14.7 FEC Tx FIFO Data Register-MBAR + 0x31A4
    • 14.7.1 FEC Rx FIFO Status Register-MBAR + 0x3188
  • 14.8 FEC Tx FIFO Status Register-MBAR + 0x31A8
    • 14.8.1 FEC Rx FIFO Control Register-MBAR + 0x318C
    • 14.8.2 FEC Rx FIFO Last Read Frame Pointer Register-MBAR + 0x3190
    • 14.8.3 FEC Rx FIFO Last Write Frame Pointer Register-MBAR + 0x3194
    • 14.8.4 FEC Rx FIFO Alarm Pointer Register-MBAR + 0x3198
    • 14.8.5 FEC Rx FIFO Read Pointer Register-MBAR + 0x319C
    • 14.8.6 FEC Rx FIFO Write Pointer Register-MBAR + 0x31A0
    • 14.8.7 FEC Reset Control Register-MBAR + 0x31C4
    • 14.8.8 FEC Transmit FSM Register-MBAR + 0x31C8
  • 14.9 Initialization Sequence
    • 14.9.1 Hardware Controlled Initialization
    • 14.9.2 User Initialization (Prior to Asserting ETHER_EN)
      • 14.9.2.1 Microcontroller Initialization
    • 14.9.3 Frame Control/Status Words
      • 14.9.3.1 Receive Frame Status Word
      • 14.9.3.2 Transmit Frame Control Word
    • 14.9.4 Network Interface Options
    • 14.9.5 FEC Frame Reception
    • 14.9.6 Ethernet Address Recognition
    • 14.9.7 Full-Duplex Flow Control
    • 14.9.8 Inter-Packet Gap Time
    • 14.9.9 Collision Handling
    • 14.9.10 Internal and External Loopback
    • 14.9.11 Ethernet Error-Handling Procedure
      • 14.9.11.1 Transmission Errors
      • 14.9.11.2 Reception Errors
• Chapter 15 Programmable Serial Controller ( PSC)
  • 15.1 Overview
    • 15.1.1 PSC Functions Overview
    • 15.1.2 Features
  • 15.2 PSC Registers-MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
    • 15.2.1 Mode Register 1 (0x00)-MR1
    • 15.2.2 Mode Register 2 (0x00) - MR2
    • 15.2.3 Status Register (0x04) - SR
    • 15.2.4 Clock Select Register (0x04) - CSR
    • 15.2.5 Command Register (0x08)-CR
    • 15.2.6 Rx Buffer Register (0x0C) - RB
    • 15.2.7 Tx Buffer Register (0x0C)-TB
    • 15.2.8 Input Port Change Register (0x10) - IPCR
    • 15.2.9 Auxiliary Control Register (0x10) - ACR
    • 15.2.10 Interrupt Status Register (0x14) - ISR
    • 15.2.11 Interrupt Mask Register (0x14)-IMR
    • 15.2.12 Counter Timer Upper Register (0x18)-CTUR
    • 15.2.13 Counter Timer Lower Register (0x1C)-CTLR
    • 15.2.14 Codec Clock Register (0x20)-CCR
    • 15.2.15 AC97 Slots Register (0x24)-AC97Slots
    • 15.2.16 AC97 Command Register (0x28)-AC97CMD
    • 15.2.17 AC97 Status Data Register (0x2C)-AC97Data
    • 15.2.18 Interrupt Vector Register (0x30)-IVR
    • 15.2.19 Input Port Register (0x34)-IP
    • 15.2.20 Output Port 1 Bit Set (0x38)-OP1
    • 15.2.21 Output Port 0 Bit Set (0x3C)-OP0
    • 15.2.22 Serial Interface Control Register (0x40)-SICR
    • 15.2.23 Infrared Control 1 (0x44)-IRCR1
    • 15.2.24 Infrared Control 2 (0x48)-IRCR2
    • 15.2.25 Infrared SIR Divide Register (0x4C)-IRSDR
    • 15.2.26 Infrared MIR Divide Register (0x50)-IRMDR
    • 15.2.27 Infrared FIR Divide Register (0x54)-IRFDR
    • 15.2.28 Rx FIFO Number of Data (0x58)-RFNUM
    • 15.2.29 Tx FIFO Number of Data (0x5C)-TFNUM
    • 15.2.30 Rx FIFO Data (0x60)-RFDATA
    • 15.2.31 Rx FIFO Status (0x64)-RFSTAT
    • 15.2.32 Rx FIFO Control (0x68)-RFCNTL
    • 15.2.33 Rx FIFO Alarm (0x6E)-RFALARM
    • 15.2.34 Rx FIFO Read Pointer (0x72)-RFRPTR
    • 15.2.35 Rx FIFO Write Pointer(0x76)-RFWPTR
    • 15.2.36 Rx FIFO Last Read Frame (0x7A)-RFLRFPTR
    • 15.2.37 Rx FIFO Last Write Frame PTR (0x7C)-RFLWFPTR
    • 15.2.38 Tx FIFO Data (0x80)-TFDATA
    • 15.2.39 Tx FIFO Status (0x84)-TFSTAT
    • 15.2.40 Tx FIFO Control (0x88)-TFCNTL
    • 15.2.41 Tx FIFO Alarm (0x8E)-TFALARM
    • 15.2.42 Tx FIFO Read Pointer (0x92)-TFRPTR
    • 15.2.43 Tx FIFO Write Pointer (0x96)-TFWPTR
    • 15.2.44 Tx FIFO Last Read Frame (0x9A)-TFLRFPTR
    • 15.2.45 Tx FIFO Last Write Frame PTR (0x9C)-TFLWFPTR
  • 15.3 PSC Operation Modes
    • 15.3.1 PSC in UART Mode
      • 15.3.1.1 Block Diagram and Signal Definition for UART Mode
      • 15.3.1.2 UART Clock Generation
      • 15.3.1.3 Transmitting in UART Mode
      • 15.3.1.4 Receiving in UART Mode
      • 15.3.1.5 Configuration Sequence for UART Mode
    • 15.3.2 PSC in Codec Mode
      • 15.3.2.1 Block Diagram and Signal Definition for Codec Mode
      • 15.3.2.2 Codec Clock and FrameSync Generation
      • 15.3.2.3 Transmitting and Receiving in “Soft Modem” Codec Mode
      • 15.3.2.4 Transmitting and Receiving in ESAI Mode (Enhanced Serial Audio Interface)
      • 15.3.2.5 Transmitting and Receiving in “Cell Phone” Mode
      • 15.3.2.6 Transmitting and Receiving in I2S Master Mode
      • 15.3.2.7 Transmitting and Receiving in SPI Mode
    • 15.3.3 PSC in AC97 Mode
      • 15.3.3.1 Block Diagram and Signal Definition for AC97 Mode
      • 15.3.3.2 Generate a reset pulse for the external AC97 Codec device
      • 15.3.3.3 AC97 Low-Power Mode
      • 15.3.3.4 Transmitting and Receiving in “Normal” AC97 Mode
      • 15.3.3.5 Transmitting and Receiving in “Enhanced” AC97 Mode
    • 15.3.4 PSC in IrDA mode
      • 15.3.4.1 PSC in SIR Mode
        • 15.3.4.1.1 Block Diagram and Signal Definition for SIR Mode
        • 15.3.4.1.2 Transmitting and Receiving in SIR Mode
        • 15.3.4.1.3 Configuration Sequence Example for SIR Mode
      • 15.3.4.2 PSC in MIR Mode
        • 15.3.4.2.1 Block Diagram and Signal Definition for MIR Mode
        • 15.3.4.2.2 Transmitting and Receiving in MIR Mode
        • 15.3.4.2.3 Serial Interaction Pulse (SIP)
        • 15.3.4.2.4 Configuration Sequence Example for MIR Mode
      • 15.3.4.3 PSC in FIR Mode
        • 15.3.4.3.1 Block Diagram and Signal Definition for FIR Mode
        • 15.3.4.3.2 Transmitting and Receiving in FIR Mode
        • 15.3.4.3.3 Configuration Sequence Example for FIR Mode
  • 15.4 PSC FIFO System
    • 15.4.1 RX FIFO
    • 15.4.2 TX FIFO
    • 15.4.3 Looping Modes
      • 15.4.3.1 Automatic Echo Mode
      • 15.4.3.2 Local Loop-Back Mode
      • 15.4.3.3 Remote Loop-Back Mode
    • 15.4.4 Multidrop Mode
• Chapter 16 XLB Arbiter
  • 16.1 Overview
    • 16.1.1 Purpose
      • 16.1.1.1 Prioritization
      • 16.1.1.2 Bus Grant Mechanism
        • 16.1.1.2.1 Bus Grant
        • 16.1.1.2.2 Parking Modes
      • 16.1.1.3 Configuration, Status, and Interrupt Generation
      • 16.1.1.4 Watchdog Functions
        • 16.1.1.4.1 Timer Functions
        • 16.1.1.4.2 Other Tenure Ending Conditions
  • 16.2 XLB Arbiter Registers-MBAR + 0x1F00
    • 16.2.1 Arbiter Configuration Register (R/W)-MBAR + 0x1F40
    • 16.2.2 Arbiter Version Register (R)-MBAR + 0x1F44
    • 16.2.3 Arbiter Status Register (R/W)-MBAR + 0x1F48
    • 16.2.4 Arbiter Interrupt Enable Register (R/W)-MBAR + 0x1F4C
    • 16.2.5 Arbiter Address Capture Register (R)-MBAR + 0x1F50
    • 16.2.6 Arbiter Bus Signal Capture Register (R)-MBAR + 0x1F54
    • 16.2.7 Arbiter Address Tenure Time-Out Register (R/W)-MBAR + 0x1F58
    • 16.2.8 Arbiter Data Tenure Time-Out Register (R/W)-MBAR + 0x1F5C
    • 16.2.9 Arbiter Bus Activity Time-Out Register (R/W)-MBAR + 0x1F60
    • 16.2.10 Arbiter Master Priority Enable Register (R/W)-MBAR + 0x1F64
    • 16.2.11 Arbiter Master Priority Register (R/W)-MBAR + 0x1F68
    • 16.2.12 Arbiter Snoop Window Register (RW)-MBAR + 0x1F70
    • 16.2.13 Arbiter Reserved Registers-MBAR + 0x1F00-1F3C, 0x1F74-1FFF
• Chapter 17 Serial Peripheral Interface ( SPI )
  • 17.1 Overview
    • 17.1.1 Features
    • 17.1.2 Modes of Operation
  • 17.2 SPI Signal Description
    • 17.2.1 Master In / Slave Out ( MISO )
    • 17.2.2 Master Out / Slave In ( MOSI )
    • 17.2.3 Serial Clock ( SCK )
    • 17.2.4 Slave-Select ( SS )
  • 17.3 SPI Registers-MBAR + 0x0F00
    • 17.3.1 SPI Control Register 1-MBAR + 0x0F00
    • 17.3.2 SPI Control Register 2-MBAR + 0x0F01
    • 17.3.3 SPI Baud Rate Register-MBAR + 0x0F04
    • 17.3.4 SPI Status Register -MBAR + 0x0F05
    • 17.3.5 SPI Data Register-MBAR + 0x0F09
    • 17.3.6 SPI Port Data Register-MBAR + 0x0F0D
    • 17.3.7 SPI Data Direction Register-MBAR + 0x0F10
  • 17.4 Functional Description
    • 17.4.1 General
    • 17.4.2 Master Mode
    • 17.4.3 Slave Mode
    • 17.4.4 Transmission Formats
      • 17.4.4.1 Clock Phase and Polarity Controls
      • 17.4.4.2 CPHA = 0 Transfer Format
      • 17.4.4.3 CPHA = 1 Transfer Format
    • 17.4.5 SPI Baud Rate Generation
    • 17.4.6 Special Features
      • 17.4.6.1 SS Output
      • 17.4.6.2 Bidirectional Mode (MOMI or SISO)
    • 17.4.7 Error Conditions
      • 17.4.7.1 Write Collision Error
      • 17.4.7.2 Mode Fault Error
    • 17.4.8 Low Power Mode Options
      • 17.4.8.1 SPI in Run Mode
      • 17.4.8.2 SPI in Wait Mode
      • 17.4.8.3 SPI in Stop Mode
    • 17.4.9 SPI Interrupts
      • 17.4.9.1 MODF Description
      • 17.4.9.2 SPIF Description
• Chapter 18 Inter-Integrated Circuit ( I 2 C )
  • 18.1 Overview
    • 18.1.1 Features
  • 18.2 I2C Controller
    • 18.2.1 START Signal
    • 18.2.2 STOP Signal
      • 18.2.2.1 Slave Address Transmission
      • 18.2.2.2 Data Transfer
      • 18.2.2.3 Acknowledge
      • 18.2.2.4 Repeated Start
      • 18.2.2.5 Clock Synchronization and Arbitration
  • 18.3 I2C Interface Registers
    • 18.3.1 I2C Address Register (MADR)-MBAR + 0x3D00 / 0x3D40
    • 18.3.2 I2C Frequency Divider Register (MFDR)-MBAR + 0x3D04 / 0x3D44
    • 18.3.3 I2C Control Register (MCR)-MBAR + 0x3D08 / 0x3D48
    • 18.3.4 I2C Status Register (MSR)-MBAR + 0x3D0C / 0x3D4C
    • 18.3.5 I2C Data I / O Register (MDR)-MBAR+ x3D10 / 0x3D50
    • 18.3.6 I2C Interrupt Control Register-MBAR + 0x3D20
    • 18.3.7 I2C Filter Register (MIFR)-MBAR + 0x3D24
  • 18.4 Initialization Sequence
  • 18.5 Transfer Initiation and Interrupt
    • 18.5.1 Post-Transfer Software Response
    • 18.5.2 Slave Mode
    • 18.5.3 Special Note on AKF
• Chapter 19 Controller Area Network ( MSCAN )
  • 19.1 Overview
  • 19.2 Features
  • 19.3 External Signals
    • 19.3.1 RXCAN - CAN Receiver Input Pin
    • 19.3.2 TXCAN - CAN Transmitter Output Pin
  • 19.4 CAN System
  • 19.5 Memory Map / Register Definition
    • 19.5.1 Module Memory Map
    • 19.5.2 Register Descriptions
    • 19.5.3 MSCAN Control Register 0 (CANCTL0)-MBAR + 0x0900 / 0x980
    • 19.5.4 MSCAN Control Register 1 (CANCTL1)-MBAR + 0x0901 / 0x981
    • 19.5.5 MSCAN Bus Timing Register 0 (CANBTR0)-MBAR + 0x0904 / 0x984
    • 19.5.6 MSCAN Bus Timing Register 1 (CANBTR1)-MBAR + 0x0905 / 0x985
    • 19.5.7 MSCAN Receiver Flag Register (CANRFLG)-MBAR+0x0908 / 0x988
    • 19.5.8 MSCAN Receiver Interrupt Enable Register (CANRIER)-MBAR + 0x0909 / 0x989
    • 19.5.9 MSCAN Transmitter Flag Register (CANTFLG)-MBAR + 0x090C / 0x98C
    • 19.5.10 MSCAN Transmitter Interrupt Enable Register (CANTIER)-MBAR+0x090D / 0x098D
    • 19.5.11 MSCAN Transmitter Message Abort Request (CANTARQ)-MBAR + 0x0910 / 0x0990
    • 19.5.12 MSCAN Transmitter Message Abort Ack (CANTAAK)-MBAR +0x0911 / 0x0991
    • 19.5.13 MSCAN Transmit Buffer Selection (CANTBSEL)-MBAR + 0x0914 /0x0991
    • 19.5.14 MSCAN ID Acceptance Control Register (CANIDAC)-MBAR + 0x0915 / 0x0995
    • 19.5.15 MSCAN Receive Error Counter Register (CANRXERR)-MBAR + 0x091C / 0x099C
    • 19.5.16 MSCAN Transmit Error Counter Register (CANTXERR)-MBAR + 0x091D/0x099D
    • 19.5.17 MSCAN ID Acceptance Registers (CANIDAR0-7)-MBAR + 0x0920 / 0x09A0
    • 19.5.18 MSCAN ID Mask Register (CANIDMR0-7)-MBAR + 0x0928 / 0x09A8
  • 19.6 Programmer’s Model of Message Storage
    • 19.6.1 Identifier Registers (IDR0-3)
    • 19.6.2 Data Segment Registers (DSR0-7)
    • 19.6.3 Data Length Register (DLR)
    • 19.6.4 MSCAN Transmit Buffer Priority Register (TBPR)-MBAR + 0x0979 / 0x09F9
    • 19.6.5 MSCAN Time Stamp Register High (TSRH)-MBAR + 0x097C / 0x09FC
    • 19.6.6 MSCAN Time Stamp Register Low (TSRL)-MBAR + 0x097D / 0x09FD
  • 19.7 Functional Description
    • 19.7.1 General
    • 19.7.2 Message Storage
      • 19.7.2.1 Message Transmit Background
      • 19.7.2.2 Transmit Structures
      • 19.7.2.3 Receive Structures
    • 19.7.3 Identifier Acceptance Filter
    • 19.7.4 Protocol Violation Protection
    • 19.7.5 Clock System
    • 19.7.6 Timer Link
    • 19.7.7 Modes of Operation
      • 19.7.7.1 Normal Modes
      • 19.7.7.2 Listen-Only Mode
    • 19.7.8 Low Power Options
      • 19.7.8.1 CPU Run Mode
      • 19.7.8.2 CPU Sleep Mode
      • 19.7.8.3 CPU Deep Sleep Mode
      • 19.7.8.4 MSCAN Sleep Mode
      • 19.7.8.5 MSCAN Initialization Mode
      • 19.7.8.6 MSCAN Power Down Mode
      • 19.7.8.7 Programmable Wake-Up Function
    • 19.7.9 Description of Interrupt Operation
      • 19.7.9.1 Transmit Interrupt
      • 19.7.9.2 Receive Interrupt
      • 19.7.9.3 Wake-Up Interrupt
      • 19.7.9.4 Error Interrupt
    • 19.7.10 Interrupt Acknowledge
    • 19.7.11 Recovery from STOP or WAIT
• Chapter 20 Byte Data Link Controller (BDLC)
  • 20.1 Overview
  • 20.2 Features
  • 20.3 Modes of Operation
  • 20.4 Block Diagram
  • 20.5 Signal Description
  • 20.6 Overview
    • 20.6.1 Detailed Signal Descriptions
      • 20.6.1.1 TXB - BDLC Transmit Pin
      • 20.6.1.2 RXB - BDLC Receive Pin
  • 20.7 Memory Map and Registers
    • 20.7.1 Overview
    • 20.7.2 Module Memory Map
    • 20.7.3 Register Descriptions
      • 20.7.3.1 BDLC Control Register 1 (DLCBCR1)-MBAR + 0x1300
      • 20.7.3.2 BDLC State Vector Register (DLCBSVR) - MBAR + 0x1300
      • 20.7.3.3 BDLC Control Register 2 (DLCBCR2) - MBAR + 0x1304
      • 20.7.3.4 BDLC Data Register (DLCBDR) - MBAR + 0x1305
      • 20.7.3.5 BDLC Analog Round Trip Delay Register (DLCBARD) - MBAR + 0x1308
      • 20.7.3.6 BDLC Rate Select Register (DLCBRSR) - MBAR + 0x1309
      • 20.7.3.7 BDLC Control Register (DLCSCR) - MBAR + 0x130C
      • 20.7.3.8 BDLC Status Register (DLCBSTAT) - MBAR + 0x130D
  • 20.8 Functional Description
    • 20.8.1 General
      • 20.8.1.1 J1850 Frame Format
      • 20.8.1.2 J1850 VPW Symbols
      • 20.8.1.3 J1850 VPW Valid/Invalid Bits & Symbols
      • 20.8.1.4 J1850 Bus Errors
    • 20.8.2 Mux Interface
      • 20.8.2.1 Mux Interface - Rx Digital Filter
    • 20.8.3 Protocol Handler
      • 20.8.3.1 Protocol Architecture
    • 20.8.4 Transmitting A Message
      • 20.8.4.1 BDLC Transmission Control Bits
      • 20.8.4.2 Transmitting Exceptions
      • 20.8.4.3 Aborting a Transmission
    • 20.8.5 Receiving A Message
      • 20.8.5.1 BDLC Reception Control Bits
      • 20.8.5.2 Receiving a Message with the BDLC module
      • 20.8.5.3 Filtering Received Messages
      • 20.8.5.4 Receiving Exceptions
    • 20.8.6 Transmitting An In-Frame Response (IFR)
      • 20.8.6.1 IFR Types Supported by the BDLC module
      • 20.8.6.2 BDLC IFR Transmit Control Bits
      • 20.8.6.3 Transmit Single Byte IFR
      • 20.8.6.4 Transmit Multi-Byte IFR 1
      • 20.8.6.5 Transmit Multi-Byte IFR 0
      • 20.8.6.6 Transmitting An IFR with the BDLC module
      • 20.8.6.7 Transmitting IFR Exceptions
    • 20.8.7 Receiving An In-Frame Response (IFR)
      • 20.8.7.1 Receiving an IFR with the BDLC module
      • 20.8.7.2 Receiving IFR Exceptions
    • 20.8.8 Special BDLC Module Operations
      • 20.8.8.1 Transmitting Or Receiving A Block Mode Message
      • 20.8.8.2 Transmitting Or Receiving A Message In 4X Mode
    • 20.8.9 BDLC Module Initialization
      • 20.8.9.1 Initialization Sequence
      • 20.8.9.2 Initializing the Configuration Bits
      • 20.8.9.3 Exiting Loopback Mode and Enabling the BDLC module
      • 20.8.9.4 Enabling BDLC Interrupts
  • 20.9 Resets
    • 20.9.1 General
• Chapter 21 Debug Support and JTAG Interface
  • 21.1 Overview
  • 21.2 TAP Link Module (TLM) and Slave TAP Implementation
  • 21.3 TLM and TAP Signal Descriptions
    • 21.3.1 Test Reset ( TRST )
    • 21.3.2 Test Clock ( TCK )
    • 21.3.3 Test Mode Select ( TMS )
    • 21.3.4 Test Data In ( TDI )
    • 21.3.5 Test Data Out ( TDO )
  • 21.4 Slave Test Reset ( STRST )
    • 21.4.1 Enable Slave-ENA [ 0 : n ]
    • 21.4.2 Select DR Link-SEL [ 0 : n ]
    • 21.4.3 Slave Test Data Out-STDO [ 0 : n ]
  • 21.5 TAP State Machines
  • 21.6 e300 Core JTAG / COP Serial Interface
  • 21.7 TLM Link DR Instructions
    • 21.7.1 TLM : TLMENA
    • 21.7.2 TLM : PPCENA
  • 21.8 TLM Test Instructions
    • 21.8.1 IDCODE
      • 21.8.1.1 Device ID Register
    • 21.8.2 BYPASS
    • 21.8.3 SAMPLE / PRELOAD
    • 21.8.4 EXTEST
    • 21.8.5 CLAMP
    • 21.8.6 HIGHZ
  • 21.9 e300 COP / BDM Interface
• Appendix A Acronyms and Terms
• Appendix B List of Registers