4 rx enables pcirer (rw) -mbar + 0x388c – Freescale Semiconductor MPC5200B User Manual
Page 334
Registers
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
10-37
10.3.3.2.4
Rx Enables PCIRER (RW) —MBAR + 0x388C
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
RC
RF
FE
CM
BE
Reserved
ME
Reserved
FEE
SE
RE
TAE
IAE
NE
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0
Reset
Controller
(RC)
User writes this bit high to put Receive Controller in a reset state. Note that other register
bits are not affected. This Reset is intended for recovery from an error condition or to reload
the Start Address when Continuous mode is selected. This Reset bit does not prohibit
register access but it must be negated in order to initiate a Restart sequence (i.e. writing the
Packet_Size register). If it is used to reload a Start Address then the Start_Add register must
be written prior to asserting this Reset bit.
1
Reset
FIFO
(RF)
The FIFO will be reset and flushed of any existing data when set high. The Reset Controller
bit and the Reset FIFO bit operate independently, but clearly both must be low for normal
operation.
2
FE
Flush enable. This is an important bit which causes a flush signal to be generated to the
Receive FIFO Controller when the end of the current packet occurs. This Flush is necessary
to insure that the Multi-Channel DMA will get all data left in the Receive FIFO. FE is active
high.
3
Continuous
mode
(CM)
User writes this bit high to activate Continuous mode. In Continuous mode the Start_Add
value is ignored at each packet restart and the PCI address is auto-incremented from one
packet to the next. Also, the Packets_Done status byte will become active, indicating how
many packets have been received since the last Reset Controller condition. If the
Continuous bit is low, software is responsible for updating the Start_Add value at each
packet Restart.
4
Bus error
Enable
(BE)
User writes this bit high to enable Bus Error indications.
for Bus Error descriptions. Normally this bit will be 0
since illegal Slave bus accesses are not destructive to register contents, although it may
indicate broken software. Note that this bit does not affect interrupt generation.
5:6
Reserved
Unused. Software should write zero to these bits.
7
Master
Enable
(ME)
This is the Receive Controller master enable signal. User must write it high to enable
operation. It can be toggled low to permit out-of-order register updates prior to generating
a Restart sequence (in which case transmission will begin when Master Enable is written
back high), but it should not be used as such in Continuous mode because it has the side
effect of resetting the Packets_Done status counter.
8:9
Reserved
Unused. Software should write zero to these bits.
10
FIFO Error
Enable
(FEE)
User writes this bit high to enable CPU Interrupt generation in the case of FIFO error
termination of a packet transmission. It may be desirable to mask CPU interrupts in the case
that Multi-Channel DMA is controlling operation, but in such a case software should poll the
status bits to prevent a possible lock-up condition.