Freescale Semiconductor MPC5200B - Manual (Page 583)

MPC5200B Users Guide, Rev. 1
15-72 Freescale Semiconductor
PSC FIFO System
Depending on whether the FIFO is set for Tx or Rx, “Alarm” and “Granularity” are measured differently, either:
• valid data bytes (Tx FIFO)
• empty bytes (Rx FIFO)
For both Tx and Rx FIFOs:
• “Alarm” specifies a threshold at which the FIFO generates an interrupt to either:
— BestComm
— CPU (alternate)
• “Granularity” specifies a threshold at which the interrupt goes away.
Each PSC provide two control lines to the BestComm system, control the transfer from and to the PSC FIFO.
The FIFOs can be accessed as follows:
• 8-bit Codec mode or UART mode
— Can access FIFOs either 1, 2, or 4 1-Byte samples at a time.
• 16-bit Codec mode:
— Can access FIFOs 1 or 2 2-Byte samples at a time.
• 32-bit and 32-Bit Codec mode
— Can access FIFOs 4-Byte samples at a time
• AC97 mode:
— Must access FIFOs one sample at a time
— In addition, when the Rx FIFO is being read, a “1” in bit 20 (21st bit of the sample) marks this sample as the first time slot of
a new frame.
Block error mode is always selected because MR1 [ERR] is hard-wired high. In block mode SR shows a logical OR of all characters received
after the last RESET ERROR STATUS command. Block mode offers a data-reception speed advantage where the software overhead of
error-checking each character cannot be tolerated. Errors are not detected until the check is done at the end of an entire message; the faulting
character is not identified.
Reading SR does not affect the FIFO. FIFO is popped only when the Rx buffer is read. If the Rx FIFO is completely full a new character is
held in the Rx shift register until space is available. However, if a second new character is received, contents of the character in the Rx shift
register is lost. The FIFO’s are unaffected, and
SR [ORERR] sets when the receiver detects the start bit of the new overrunning character.
To support flow control, the receiver can be programmed to automatically negate and assert
RTS
. In which case, the receiver automatically
negates RTS when a valid start bit is detected and the FIFO stack is full. The receiver asserts RTS when a FIFO position becomes available.
Overrun errors can be prevented by connecting RTS to the CTS input of the transmitting device.
NOTE
The receiver can still read characters in the FIFO stack if the receiver is disabled. If the receiver is
reset, the FIFO stack,
RTS control, all receiver status bits, and interrupt requests are reset. No more
characters are received until the receiver is re-enabled.