8 fec mii speed control register-mbar + 0x3044, Fec mii speed control register—mbar + 0x3044 -18, Fec mii speed control register -18 – Freescale Semiconductor MPC5200B User Manual
Page 483: Section 14-16, fec mii speed control register
MPC5200B Users Guide, Rev. 1
14-18
Freescale Semiconductor
FEC Registers—MBAR + 0x3000
user. When the write management frame operation is complete, the MII_DATAIO_COMPL interrupt is generated. At this time the MII_DATA
register contents match the original value written.
To generate an MII Management Interface read frame (read a PHY register) the user must write the following to the MII_DATA register
(DATA field content is "don’t care"):
{01 10 PHYAD REGAD 10 XXXX}
Writing this pattern causes control logic to shift out data in the MII_DATA register following a preamble generated by the control state
machine. During this time, the MII_DATA register contents are altered as the contents are serially shifted, and is unpredictable if read by the
user. When the read management frame operation is complete, the MII_DATAIO_COMPL interrupt is generated. At this time the MII_DATA
register contents matches the original value written, except for the DATA field whose contents have been replaced by the value read from the
PHY register.
If the MII_DATA register is written while frame generation is in progress, frame contents are altered. Software should use the MII_STATUS
register and/or the MII_DATAIO_COMPL interrupt to avoid writing to the MII_DATA register while frame generation is in process.
14.5.8
FEC MII Speed Control Register—MBAR + 0x3044
The MII_SPEED register provides MII clock (MDC pin) frequency control. This allows dropping the MII management frame preamble and
provides observability (intended for manufacturing test) of an internal counter used in generating an MDC clock signal.
Table 14-16. FEC MII Speed Control Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
DIS_PREAMBLE
MII_SPEED
Rsvd
W
RESET: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0