26 infrared mir divide register (0x50)-irmdr, Infrared mir divide register (0x50)—irmdr -30, Infrared mir divide register (0x50)—irmdr – Freescale Semiconductor MPC5200B User Manual
Page 546
PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
15-35
15.2.26
Infrared MIR Divide Register (0x50)—IRMDR
This register set the MIR mode Baud rate. This register is reserved in other modes.
Table 15-49. Infrared SIR Divide Register (0x48) for SIR Mode
msb 0
1
2
3
4
5
6
7 lsb
R
IRSTIM[0:7]
W
RESET:
0
0
1
1
0
1
1
0
Table 15-50. Infrared SIR Divide Register (0x48) for other Modes
msb 0
1
2
3
4
5
6
7 lsb
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
Bit
Name
Description
0:7
IRSTIM
SIR—Timer counter value for 1.6us pulse
In SIR mode, this is used to make 1.6
µs pulse when SPUL in the
is high. This value
should be set so that
IPB clock period * IRSTIM = 1.6
µs
Reset value is 54(0x36) and this is for 33 MHz bus clock.
other Modes—Reserved
Table 15-51. Infrared MIR Divide Register (0x50) for MIR Mode
msb 0
1
2
3
4
5
6
7 lsb
R
FREQ
M_FDIV
W
RESET:
0
0
0
0
0
0
0
0
Table 15-52. Infrared MIR Divide Register (0x50) for other Modes
msb 0
1
2
3
4
5
6
7 lsb
R
Reserved
W
RESET
:
0
0
0
0
0
0
0