Freescale Semiconductor MPC5200B - Manual (Page 468)

Modes of Operation
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 14-3
• Automatic internal flushing of the Rx FIFO for runts (collision fragments) and address recognition rejects (no processor bus
utilization).
• Address recognition
— Frames with broadcast address may be always accepted or always rejected
— Exact match for single 48-bit individual (unicast) address
— Hash (64-bit hash) check of individual (unicast) addresses
— Hash (64-bit hash) check of group (multicast) addresses
— Promiscuous mode
14.2 Modes of Operation
The primary operational modes are described in this section.
14.2.1 Full- and Half-Duplex Operation
This is determined by the X_CNTRL register FDEN bit. Full-duplex mode is intended for use on point to point links between switches or end
node to switch. Half-duplex mode is used in connections between an end node and a repeater or between repeaters.
Full-duplex flow control is an option that may be enabled in full-duplex mode.
14.2.2 10Mbps and 100Mbps MII Interface Operation
The MAC-PHY interface operates in MII mode by asserting the R_CNTRL register MII_MODE bit. MII is the media independent interface
defined by the 802.3 standard for 10/100 Mbps operation.
Speed of operation is determined by the TX_CLK and RX_CLK pins, which are driven by the transceiver. The transceiver either
auto-negotiates the speed or it may be controlled by software using the serial management interface (MDC/MDIO pins) to the transceiver.
14.2.3 10Mbps 7-Wire Interface Operation
If the external transceiver supports 10 Mbps only and uses a 7-wire style interface then deassert the R_CNTRL register MII_MODE bit in the
R_CNTRL register. This style of interface is not defined by the 802.3 standard, but instead is an industry standard.
14.2.4 Address Recognition Options
The options supported are promiscuous, broadcast reject, individual address hash or exact match and multicast hash match. Refer to the
R_CNTRL register for address recognition programming.
14.2.5 Internal Loopback
Internal loopback mode is selected using the R_CNTRL register LOOP bit.
14.3 I/O Signal Overview
This section defines the FEC-to-chip pin I/O. The FEC network interface supports multiple options. One is the MII option that requires 18
I/O pins and supports both data and an out-of-band serial management interface to the PHY (transceiver) device. The MII option supports
both 10 and 100 Mbps Ethernet rates. The second is referred to as the 7-wire interface and supports only 10 Mbps Ethernet data. The 7-wire
interface uses a subset of the MII signals.
Table 14-1 shows the network interface signals and lists 18 signals, all of which are used for the 10/100 MII interface.
NOTE
The MDIO pin is bidirectional and corresponds to the FEC block MDI, MDO and MDIO pins. The
7-wire interface option uses a subset of these signals.
Table 14-1. Signal Properties
Signal Name Chip Pin Function Reset State
tx_en ETH0 MII—transmit data valid output
7-wire—transmit data valid output
0
tdata[0] ETH1 MII—transmit data bit 0 output
7-wire—transmit data output