Freescale Semiconductor MPC5200B - Manual (Page 661)

MPC5200B Users Guide, Rev. 1
19-22 Freescale Semiconductor
Programmer’s Model of Message Storage
— CANIDMR7
19.6 Programmer’s Model of Message Storage
The following section details the organization of the receive and transmit message buffers and the associated control registers. For reasons of
programmer interface simplification, the receive and transmit message buffers have the same outline. Each message buffer allocates 16 bytes
in the memory map containing a 13 byte data structure. An additional Transmit Buffer Priority Register (TBPR) is defined for the transmit
buffers. Within the last two bytes of this memory map the MSCAN stores a special 16-bit time stamp, which is sampled from an internal timer
after successful transmission or reception of a message. This feature is only available for transmit and receiver buffers, if the TIME bit is set
(
Section 19.5.3, MSCAN Control Register 0 (CANCTL0)—MBAR + 0x0900 / 0x980 ). The Time Stamp register is written by the MSCAN. The
CPU can only read these registers.
Figure 19-27 shows the common 13 byte data structure of receive and transmit buffers for extended identifiers. The mapping of standard
identifiers into the IDR registers is shown in Figure 19-28 . All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM
based implementation
1
.All reserved or unused bits of the receive and transmit buffers are always read ‘x’.
Table 19-26. Message Buffer Organization
Addr Register Name
$__00,$__80 Identifier Register 0
$__01,$__81 Identifier Register 1
$__04,$__844 Identifier Register 2
$__05,$__85 Identifier Register 3
$__08,$__88 Data Segment Register 0
$__09,$__89 Data Segment Register 1
$__0C,$__8C Data Segment Register 2
$__0D,$__8D Data Segment Register 3
$__10,$__90 Data Segment Register 4
$__11,$__91 Data Segment Register 5
$__14,$__94 Data Segment Register 6
$__15,$__95 Data Segment Register 7
$__18,$__98 Data Length Register
$__19,$__99 Transmit Buffer Priority Register
a
a
Not Applicable for Receive Buffers
$__1C,$__9C Time Stamp Register (High Byte)
b
b
Read-Only for CPU
$__1D,$__9D Time Stamp Register (Low Byte) c
c Read-Only for CPU
1. Exception: The Transmit Priority Registers are “0” out of reset
Table 19-27. Receive / Transmit Message Buffer Extended Identifier
Register Bit 7 6 5 4 3 2 1 Bit 0 ADDR
IDR0 Read: ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 $__00
Write:
= Unused a