Freescale Semiconductor MPC5200B - Manual (Page 688)

Memory Map and Registers
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 20-9
0 = When cleared, digital filter input is connected to receive pin (RXB) and the transmitter output is connected to the transmit pin
(TXB). The BDLC module is taken out of Digital Loopback Mode and can now drive and receive from the J1850 bus normally.
After writing DLOOP to zero, the BDLC module requires the bus to be idle for a minimum of an End of Frame symbol time before
allowing a reception of a message. The BDLC module requires the bus to be idle for a minimum of an Inter-Frame Separator symbol
time before allowing any message to be transmitted.
NOTE
The DLOOP bit is a fault condition aid and should never be altered after the BDLC Data Register is
loaded for transmission. Changing DLOOP during a transmission may cause corrupted data to be
transmitted onto the J1850 network.
4XE
—
4X Mode Enable (Bit 5)
This bit determines if the BDLC operates at normal transmit and receive speed (10.4 kbps) or in 4X Mode at 41.6 kbps. This feature is
useful for fast download of data into a J1850 node for diagnostic or factory programming of the node.
1 = When set, the BDLC module is put in 4X (41.6 kbps) operation.
0 = When cleared, the BDLC module transmits and receives at 10.4 kbps. Reception of a BREAK symbol automatically clears this
bit and sets the symbol invalid or out of range flag BDLC State Vector Register = $1C).
The effect of 4X receive operation on receive symbol timing boundaries is described in Section 20.8.1.3, J1850 VPW Valid/Invalid Bits
& Symbols .
NBFS
—
Normalization Bit Format Select (Bit 4)
This bit controls the format of the Normalization Bit (NB). SAE J1850 strongly encourages the use of an active long: ‘0’ for In-Frame
Responses containing CRC and active short, ‘1’ for In-Frame Responses without CRC.
1 = NB that is received or transmitted is a ‘0’ when the response part of an In-Frame Response (IFR) ends with a CRC byte. NB
that is received or transmitted is a ‘1’ when the response part of an In-Frame Response (IFR) does not end with a CRC byte.
0 = NB that is received or transmitted is a ‘1’ when the response part of an In-Frame Response (IFR) ends with a CRC byte. NB
that is received or transmitted is a ‘0’ when the response part of an In-Frame Response (IFR) does not end with a CRC byte.
TEOD
—
Transmit End of Data (Bit 3)
This bit is set by the programmer to indicate the end of a message being sent by the BDLC. It will append an 8-bit CRC after completing
transmission of the current byte in the Tx Shift Register followed by the EOD symbol. If the transmit shadow register (refer to
Section
20.8.3.1, Protocol Architecture for a description of the transmit shadow register) is full when TEOD is set, the CRC byte and EOD will
be transmitted after the current byte in the Tx Shift Register and the byte in the Tx Shadow Register have been transmitted. Once TEOD
is set, the transmit data register empty flag (TDRE) in the BDLC State Vector Register (BDLC State Vector Register) is cleared to allow
lower priority interrupts to occur. This bit is also used to end an IFR. Bits TSIFR, TMIFR1, and TMIFR0 determine whether a CRC byte
is appended before EOD transmission for IFRs.
1 = Transmit EOD symbol.
0 = The TEOD bit will be automatically cleared after the first CRC bit is sent, or if an error or loss of arbitration is detected on the
bus. When TEOD is used to end an IFR transmission, TEOD is cleared when the BDLC receives back a valid EOD symbol, or an
error condition or loss of arbitration occurs.
TSIFR, TMIFR1, TMIFR0
—
Transmit In-Frame Response Control (Bits 2-0)
These three bits control the type of In-Frame Response being sent. The programmer should not set more than one of these control bits to
a one at any given time. However, if more than one of these three control bits are set to one, the priority encoding logic will force the
internal register bits to a known value as shown in the following table. But, when these bits are read, they will be the same as written
earlier. For instance, if “011” is written to TSIFR, TMIFR1, TMIFR0, then internally, they’ll be encoded as “010”. However, when these
bits are later read back, it’ll still be “011”.
Table 1-2. Transmit In-Frame Response Control Bit Priority Encoding
WRITE READ ACTUAL (internal register)
TSIFR TMIFR1 TMIFR0 TSIFR TMIFR1 TMIFR0 TSIFR TMIFR1 TMIFR0
0 0 0 0 0 0 0 0 0
1 X X 1 X X 1 0 0
0 1 X 0 1 X 0 1 0
0 0 1 0 0 1 0 0 1