Freescale Semiconductor MPC5200B User Manual
Page 156
CDM Registers
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
5-23
5.5.14
PSC6 (IrDA) Mclock Config Register—MBAR + 0x0234
This register controls the generation of the Mclock for PSC6. Before modify the register value the divider must be disabled.
Table 5-21. CDM PSC6 Mclock Config
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
Write 0
W
RESET:
0
0
0
0
0
0
0
—
0
0
0
0
0
0
0
—
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Mc
loc
k
Enab
le
Reserved
Write 0
MclkDiv[8:0]
W
RESET:
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Bit
Name
Description
0–15
—
Reserved for future use. Write 0.
16
Mclock Enable
PSC6 Mclock enable.
bit=0:Turns off internally generated Mclock.
bit=1:Turns on internally generated Mclock.
17-22
—
Reserved for future use. Write 0.
23-31
MclkDiv[8:0]
The counter divide the f
system
frequency by MclkDiv+1. A vallue of 0x00 in this
register turns off internally generated Mclock.
For example, a value of 7 in this register, where fsystem clock is at a frequency of
528MHz would result in a Mclock rate of 528/8, or 66 MHz.
Note:
f
system
clock is always 12 or 16 times the reference clock, sys_xtal_in,
depending on sys_pll_cfg_0 at reset.