Freescale Semiconductor MPC5200B - Manual (Page 301)

MPC5200B Users Guide, Rev. 1
10-4 Freescale Semiconductor
Registers
10.3 Registers
MPC5200B has several sets of registers that control and report status for the different interfaces to the PCI controller: PCI Type 0
Configuration Space Registers, General Status/Control Registers, and Communication Sub-System Interface Registers. All of these registers
are accessible as offsets of MBAR (the PCI interface is located starting at offset 0x0D00 relative to the MBAR register’s value, while the
BestComm interface starts at offset 0x3800). As an XL bus master, an external PCI bus master can access MBAR space for register updates
and the internal SRAM.
NOTE
PCI_RST is controlled by a bit in the register space and must first be cleared before external PCI
devices wake-up. In other words, an external PCI master cannot load configuration software across
the PCI bus until this bit is cleared by internal means.
All registers are accessible at an offset of MBAR in the memory space. There are two module offsets for PCI configuration space. One is
allocated to the Communication Sub-System Interface registers and the other to all other PCI Controller Registers including the standard Type
0 PCI Configuration Space. Software reads from unimplemented registers return 0x00000000 and writes have no effect. See
Section 3.2,
Internal Register Memory Map for module offsets and descriptions of module responses.
Table 10-2. PCI Register Map
Register
Offset
Mnemonic Name
PCI Type 0 Configuration Registers
0x00 PCIIDR Device ID/Vendor ID
0x04 PCISCR Status/Command
0x08 PCICCRIR Class Code/Revision ID
0x0C PCICR1 Configuration 1Register
0x10 PCIBAR0 Base Address Register 0
0x14 PCIBAR1 Base Address Register 1
0x18 Reserved
...
0x24
0x28 PCICCPR Cardbus CIS Pointer
0x2C PCISID Subsystem ID/Subsystem Vendor ID
0x30 PCIERBAR Expansion ROM
0x34 PCICPR Capabilities Pointer
0x38 Reserved
0x3C PCICR2 Configuration 2 Register
0x40 Reserved
...
0x5C
General Control/Status Registers
0x60 PCIGSCR Global Status/Control Register
0x64 PCITBATR0 Target Base Address Translation Register 0
0x68 PCITBATR1 Target Base Address Translation Register 1
0x6C PCITCR Target Control Register
0x70 PCIIW0BTAR Initiator Window 0 Base/Translation Address Register