Ictl critical interrupt status all register – Freescale Semiconductor MPC5200B User Manual
Page 174
Interrupt Controller
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
7-15
7.2.4.10
ICTL Critical Interrupt Status All Register—MBAR + 0x0528
21:23
CSe
Critical Status Encoded—makes a singular indication of the current critical interrupt (3bits
indicating 1 of 4 possible interrupts).
The msb operates as a Flag bit, as described above. This msb can also be written to 1 to
force a re-evaluation of the critical interrupt sources.
00 = IRQ input pin is the source. See Note
2
.
01 = Slice Timer 0 is the source.
10 = HI_int is the source. See Note
3
.
11 = CCS module is the source. WakeUp from deep-sleep. See Note
4
.
24:30
—
Reserved
31
CEbSh
Critical Enable bar Shadow bit—this is a special bit that shadows the setting programmed
into ICTL External Enable and External Types Register. This bit indicates whether Critical
interrupt sources have or have not been directed to the normal INT e300 core pin.
If Critical interrupts are directed to INT (CEbSh = 1), to detect higher priority interrupt
sources, INT ISR must always parse the CSe prior to MSe or PSe. All other processing
remains the same.
This shadow bit is provided here so a single read to this register can obtain all necessary
information to make the interrupt source determination.
Note:
1.
For Main sources 1, 2, and 3 that represent IRQ[1:3] respectively, if the IRQ pin is set as edge sensitive, it is REQUIRED
that the MSe flag bit be cleared (i.e., written to 1) or the appropriate ECLR bit in ICTL External Enable and External
Types Register be set to clear this interrupt indication. Only one method should be used, not both (this limit is only true
for multiple edge-sensitive IRQ inputs).
2.
For IRQ[0] set as edge sensitive, it is REQUIRED that either the CSe flag bit be cleared (i.e., written to 1) or the
ECLR[0] bit in
ICTL External Enable and External Types Register
be set to clear this interrupt indication.
You can do both if desired, and you can do it regardless of the IRQ[0] interrupt type.
3.
This indicates a peripheral source programmed for HI bank priority is the source. It is necessary to parse the PSe value
to determine the peripheral source module.
4.
For recovery from deep-sleep mode, it is necessary to acknowledge this WakeUp interrupt by writing 1 to the msb of
this field (CSe). Only then does the CCS module release it's power-down internal signal and let MPC5200B operate
normally.
Table 7-13. ICTL Critical Interrupt Status All Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
CSa
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description