3 cdm bread crumb register-mbar + 0x0208, 4 cdm configuration register-mbar + 0x020c, Cdm bread crumb register—mbar + 0x0208 – Freescale Semiconductor MPC5200B User Manual
Page 147: Cdm configuration register
MPC5200B Users Guide, Rev. 1
5-14
Freescale Semiconductor
CDM Registers
5.5.3
CDM Bread Crumb Register—MBAR + 0x0208
The CDM Bread Crumb Register is a 32-bit register that is not reset. Its purpose is to let firmware designers leave some status code before
entering a reset condition. Since this register is never reset, the value written is available after the reset condition has ended. There is no
additional functionality to this register.
5.5.4
CDM Configuration Register—MBAR + 0x020C
The CDM Configuration Register contains 3 bits that set IPB_CLK and PCI_CLK ratios.
27
ppc_pll_cfg_0
e300 Core core pll config pins. See also
28
ppc_pll_cfg_1
29
ppc_pll_cfg_2
30
ppc_pll_cfg_3
31
ppc_pll_cfg_4
Table 5-10. CDM Bread Crumb Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
CDM Bread Crumb Register (Never Reset)
W
RESET:
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
CDM Bread Crumb Register (Never Reset)
W
RESET:
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table 5-11. CDM Configuration Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
Write 0
ddr_
mode
Reserved
Write 0
xlb_
cl
k_sel
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
V
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
Write 0
ipb_
cl
k_sel
Reserved
Write 0
pci_
clk_sel
W
RESET:
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
Bit
Name
Description