8 fec transmit fsm register-mbar + 0x31c8, 9 initialization sequence, 1 hardware controlled initialization – Freescale Semiconductor MPC5200B User Manual
Page 499: Fec transmit fsm register—mbar + 0x31c8 -34, Initialization sequence -34, Hardware controlled initialization -34, Fec transmit fsm register -34, Ether_en de-assertion affect on fec -34, Section 14-39, fec transmit fsm register, Table 1-1
MPC5200B Users Guide, Rev. 1
14-34
Freescale Semiconductor
Initialization Sequence
14.8.8
FEC Transmit FSM Register—MBAR + 0x31C8
The transmit finite state machine register (XMIT_FSM) controls operation of appending CRC. Typical use is enabled and CRC is appended.
14.9
Initialization Sequence
This section describes which registers are hardware reset, which are reset by the FEC and what locations the user must initialize prior to
enabling the FEC.
14.9.1
Hardware Controlled Initialization
Some registers in the FEC are reset by internal logic. Specifically those registers are control logic that generate interrupts, cause outputs to be
asserted and, in general, configuration control bits.
Other registers are reset when the ETHER_EN bit is not asserted (i.e., cleared). To halt operation ETHER_EN is deasserted by either a hard
reset or by software. By deasserting ETHER_EN configuration control registers such as X_CNTRL and R_CNTRL are not reset, but the entire
data path is reset.
shows the effect deasserting ETHER_EN has on Ethernet MAC operation and registers.
7
RCTL[0]
0 = Disable fec_enable as a reset to FIFO controllers.
1 = Enable fec_enable as a reset to FIFO controllers.
8:31
---
Reserved
Table 14-39. FEC Transmit FSM Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
XFS
M
[1
]
XFS
M
[0
]
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:5
—
Reserved
6
XFSM[1]
0 = Do not append CRC.
1 = Append CRC (typical use).
7
XFSM[0]
0 = Disable CRC FSM.
1 = Enable CRC FSM (typical use is enabled).
8:31
---
Reserved
Table 14-40. ETHER_EN De-Assertion Affect on FEC
Register/Machine
Reset Value
XMIT block
Transmission Aborted (bad CRC appended)
RECV block
Receive activity aborted
Tx/Rx FIFO
Reset control logic dependent on reset_cntrl
Table 1-1.
Bits
Name
Description