Freescale Semiconductor MPC5200B - Manual (Page 541)

MPC5200B Users Guide, Rev. 1
15-30 Freescale Semiconductor
PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
15.2.22 Serial Interface Control Register (0x40) — SICR
This register sets the main operation mode.
6 RES Assert RES output.
0 = No operation
1 = Negates output port RES, (RES becomes 1).
7 RTS AC97—Reserved
other Modes—Assert RTS output.
0 = No operation
1 = Negates output port RTS, (RTS becomes 1).
Table 15-44. Serial Interface Control Register (0x40) for all Modes
msb 0 1 2 3 4 5 6 7
R ACRB AWR DTS1 SHDIR SIM[3:0]
W
RESET: 0 0 0 0 0 0 0 0
8 9 10 11 12 13 14 15
R GenClk I2S ClkPol SyncPol CellSlave Cell2xClk ESAI EnAC97
W
RESET: 0 0 0 1 0 0 0 0
16 17 18 19 20 21 22 23 lsb
R SPI MSTR CPOL CPHA UseEOF Disable_EOF Reserved
W
RESET: 0 0 0 0 0 0 0 0
Bit Name Description
0 ACRB AC97—AC97 Cold Reset to the transceiver in PSC. This bit was prepared for backward
compatibility with the MCF5407 USART. It is recommended to use
OP1 and OP0 registers to
set and to reset AC97 reset line.
0 = The transceiver recovers from low power mode in AC97.
1 = The transceiver stays in the current state.
other Modes—Reserved
1 AWR AC97—AC97 Warm Reset (to the PSC and off-chip AC97 Codec)
0 = AC97 warm reset is negated. RTS output functions normally as the AC97 FrameSync.
1 = Force “1” on RTS output, which is used as the AC97 FrameSync, and the PSC recovers
from AC97 power down mode.
other Modes—Reserved
2 DTS1 Codec—Delay of time slot #1.
0 = first bit of first time slot of a new frame starts at the rising edge of FrameSync.
1 = first bit of first time slot of a new frame starts one bit clock cycle after the rising edge of
FrameSync.
other Modes—Reserved
Bit Name Description