Freescale Semiconductor MPC5200B User Manual
Page 322
Registers
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
10-25
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
Max_Beats
Reserved
W
Reserved
DI
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:3
Reserved
Unused. Software should write zero to these bits.
4:7
PCI_cmd
The user writes this field with the desired PCI command to present during the address
phase of each PCI transaction. The default is Memory Write. This field is not checked for
consistency and if written to an illegal value, unpredictable results will occur. If not using
the default value, the user should write this register only once prior to any packet Restart.
8:15
Max_Retries
The user writes this field with the maximum number of retries to permit “perpacket”. The
retry counter is reset when the packet completes normally or is terminated by a master
abort, target abort, or an abort due to exceeding the retry limit. A slow or malfunctioning
Target might issue infinite disconnects and therefore permanently tie up the PCI bus.
A finite (0x01 to 0xff) Max_Retries value will detect this condition and generate an interrupt.
Setting Max_Retries to 0x00 will not generate any interrupt.
16:20
Reserved
Unused bits. Software should write zero to these bits.
21:23
Max_Beats
The user writes this register with the desired number of PCI data beats to attempt on each
PCI transaction. The default setting of 0 represents the maximum of eight beats per
transaction. The transmit controller will wait until sufficient bytes are in the Transmit FIFO
to support the indicated number of beats (NOTE: Each beat is four bytes). In the case that
a packet is nearly complete and less than the Max_Beats number of bytes remain to
complete the packet, the Transmit Controller will issue single-beat transactions
automatically until the packet is finished.
24:26
Reserved
Unused. Software should write zero to these bits.
27
Word Transfer
(W)
The user writes this register to disable the two high byte enables of the PCI bus during
SCPCI initiated write transactions. The default setting is 0, enable all 4 byte enables.
28:30
Reserved
Unused. Software should write zero to these bits.
31
Disable address
Incrementing
(DI)
The user writes this register to disable PCI address incrementing between transactions.
The default setting is 0, incrementing the address by 4 (4 byte data bus).
Note: This feature is recommended when an external FIFO (with a fixed address) must be
written.