Freescale Semiconductor MPC5200B - Manual (Page 712)

Functional Description
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 20-33
Figure 20-13. Basic BDLC Transmit Flowchart
20.8.5 Receiving A Message
The design of the BDLC module makes it especially easy to use for receiving messages off of the SAE J1850 bus. When the first byte of a
message comes in, the BDLC State Vector Register will indicate to the CPU that a byte has been received. As each successive byte is received,
that will in turn be reflected in the BDLC State Vector Register. When the message is complete and the EOF has been detected on the bus, the
BDLC State Vector Register will reflect this, indicating that the message is complete.
The basic steps required for receiving a message from the SAE J1850 bus are outlined below. For more information on receiving IFR bytes,
refer to
Section 20.8.7, Receiving An In-Frame Response (IFR) .
Enter BDLC module Transmit
Routine
Write first message
byte to be transmitted
into DLCBDR
Is DLCBSVR = $00?
Yes
No
Load next byte to be
transmitted into DLCBDR
(clears TDRE)
Is DLCBSVR = $1C?
Yes
No
Is DLCBSVR = $14?
Yes
No
Is DLCBSVR = $10?
Yes
No
(TDRE)
(LOA)
(Invalid Symbol)
Attempt another
Yes
No
transmission?
Is this the last
Yes
No
byte?
A
A
Jump to BDLC module
Receive Routine
Once BDLC module detects
EOF, transmit
Set TEOD bit
in DLCBCR2
attempt is complete
Yes
No
IFR Received?
Jump to Receive IFR
Handling Routine
Exit BDLC module Transmit
Routine
B
B
C
C
Go to BDLC module
BREAK/Error Handling
Routine
For interrupt driven systems,
this marks the beginning of the
transmit section of the BDLC
module interrupt service
routine
NOTE: The EOF and CRC Error interrupts
are handled in the BDLC module Receive
Routine