2 e300 core clock domain, E300 core clock domain – Freescale Semiconductor MPC5200B User Manual
Page 138
MPC5200B Clock Domains
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
5-5
shows the typical clock ratios with a 33.0 MHz clock input on the SYS_XTAL_IN pin and a System PLL divide value 16
(sys_pll_cfg[0] = 0).
NOTE
Frequency ranges in
and
represent possible ranges of operation. A variety of
conditions may prevent the part from actually performing at these frequency ranges. For data relating
to actual performance, see Section A.2, AC Timing.
5.3.2
e300 Core Clock Domain
The e300 Core has its own APLL and clock domain, which is separate from, but synchronous with, the rest of the chip. The reference for the
processor APLL is the XLB clock. The e300 Core can run at all integer and half-integer multiples of xlb_clk from 2x to 8x (i.e., 2x, 2.5x, 3x,
3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x) to a maximum frequency of 396MHz.
shows the available core frequencies based
on the xlb_clk frequency range.
NOTE
These frequencies are not guaranteed. Actual operation frequencies will depend on silicon
characterization and operating conditions.
Table 5-4. Typical System Clock Frequencies
f
system
[MHz]
XLB Clock
[MHz]
IPB CLock
[MHz]
PCI CLOCK
[MHz]
Clock Ratio
XLB:IPB:PCI
528.0
132.0
132.0
66.0
4:4:2
33.0
4:4:1
66.0
66.0
4:2:2
33.0
4:2:1
33.0
33.0
4:1:1
66.0
66.0
66.0
2:2:2
33.0
2:2:1
33.0
33.0
2:1:1