Freescale Semiconductor MPC5200B - Manual (Page 744)

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MPC5200B Users Guide, Rev. 1
Freescale Semiconductor A-5
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Harvard architecture . . . . . . . An architectural model featuring separate caches for instruction and data.
HC, Hc . . . . . . . . . . . . . . . . . Host Controller
HCD . . . . . . . . . . . . . . . . . . . Host Controller Driver
HDLC . . . . . . . . . . . . . . . . . . High-level Data Link Control—a transmission protocol used at the data link layer (layer 2) of the OSI seven
layer model for data communications. The HDLC protocol embeds information in a data frame that allows
devices to control data flow and correct errors.
. . . . . . . . . . . . . . . . . . . . . . . HDLC is an ISO standard developed from the Synchronous Data Link Control (SDLC) standard proposed by
IBM.
HEC . . . . . . . . . . . . . . . . . . . Header Error Control
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ICTL . . . . . . . . . . . . . . . . . . . Interrupt Controller
IEEE . . . . . . . . . . . . . . . . . . . Institute of Electrical and Electronics Engineers
IEEE754 . . . . . . . . . . . . . . . . A standard, written by the Institute of Electrical and Electronics Engineers, which defines operations and
representations of binary floating-point arithmetic.
I 2 C. . . . . . . . . . . . . . . . . . . . . Inter-Integrated Circuit
IC . . . . . . . . . . . . . . . . . . . . . Input Capture. Also see OC and PWM.
IDE . . . . . . . . . . . . . . . . . . . . Integrated Drive Electronics—Interface for connecting additional hard drives to a computer.
IDL . . . . . . . . . . . . . . . . . . . . Inter-chip Digital Link
IDMA . . . . . . . . . . . . . . . . . . Internal Direct Memory Access
Illegal instructions. . . . . . . . . A class of instructions not implemented for a particular microprocessor. These include instructions not defined
by the PowerPC architecture. In addition:
. . . . . . . . . . . . . . . . . . . . . . . For 32-bit implementations, instructions defined for 64-bit implementations only are considered illegal
instructions.
. . . . . . . . . . . . . . . . . . . . . . . For 64-bit implementations, instructions defined for 32-bit implementations only are considered illegal
instructions.
Implementation . . . . . . . . . . . A particular processor that conforms to the PowerPC architecture, but may differ from other
architecture-compliant implementations; for example, in design, feature set, and implementation of optional
features. The PowerPC architecture has many different implementations.
Implementation-dependent . . An aspect of a feature in a processor’s design that is defined by a processor’s design specifications, rather than
by the PowerPC architecture.
Implementation-specific . . . . An aspect of a feature in a processor’s design that is not required by the PowerPC architecture, but for which
the PowerPC architecture may provide concessions to ensure processors implementing the feature do so
consistently.
Imprecise exception . . . . . . . A type of synchronous exception that is allowed not to adhere to the precise exception model. See also Precise
exception. The PowerPC architecture lets only floating-point exceptions be handled imprecisely.
individual serial controllers . SCC, SMC, SPI, I 2 C, and USB—these individual serial controllers request service from the CPM.
Internal bus . . . . . . . . . . . . . . bus that connects the core and System Interface Unit (SIU).
Instruction latency. . . . . . . . . The total number of clock cycles necessary to execute an instruction and make ready the results of that
instruction.
int . . . . . . . . . . . . . . . . . . . . . interrupt
Interrupt . . . . . . . . . . . . . . . . An asynchronous exception—on processors that use the PowerPC architecture, interrupts are a special case of
exceptions. See also asynchronous exception.
IP. . . . . . . . . . . . . . . . . . . . . . Intellectual Property—a unique number that identifies a particular computer in a network of computers. The IP
part of TCP/IP; a protocol used to route a data packet from its source to its destination.
IPBI, IP bus. . . . . . . . . . . . . . IP Bus Interface—the Intellectual Property Bus Interface
IR . . . . . . . . . . . . . . . . . . . . . Infrared
IR . . . . . . . . . . . . . . . . . . . . . Instruction Register
IrDA, IRDA . . . . . . . . . . . . . Infrared Data Association
IRQ . . . . . . . . . . . . . . . . . . . . Interrupt Request
ISI . . . . . . . . . . . . . . . . . . . . . Instruction Storage Interrupt
ITLB . . . . . . . . . . . . . . . . . . . Instruction Translation Lookaside Buffer
IU . . . . . . . . . . . . . . . . . . . . . Integer Unit