Arbiter snoop window register (rw)—mbar + 0x1f70 – Freescale Semiconductor MPC5200B User Manual
Page 599
MPC5200B Users Guide, Rev. 1
16-12
Freescale Semiconductor
XLB Arbiter Registers—MBAR + 0x1F00
16.2.12
Arbiter Snoop Window Register (RW)—MBAR + 0x1F70
The Arbiter Snoop Window Register is used by the PCI, BestComm, and USB Host interfaces to the XLB. This register dictates the size of
an address range in memory that will allow or prohibit address snooping. Each master interface (MBI) monitors this register and determines
if the master’s address transferred to the XLB should be sent with gbl_b signal assertion.
The benefit of this implementation of a system-wide address snooping control mechanism is that address ranges that need not be
cache-coherent will not be snooped by the core. Under certain conditions, the core can assert an internal signal, ARTRY, when it is too busy
to check the cache for a snooped address on the bus. Therefore, by specifying an address range that doesn’t require snooping, the number of
core-initiated “busy ARTRY” scenarios can be minimized, and the subsequent time penalty to eventually retry the transaction is avoided. The
quantity of this incremental system performance increase is dependant upon the loading of core (especially as related to the caches), and the
average number of accesses to the designated regions of the snoop window.
The MPC5200B implementation of this address snooping control is shown in the figure below. At the start of a master’s address tenure, the
master interface decodes the address and determines if it needs to be snooped, based on the configuration of the Arbiter Snoop Window
Register. If the transaction requires snooping, the gbl_b signal is asserted; otherwise, gbl_b is negated. However, before the gbl_b signal
reaches the XLB for the address tenure, it is gated by a mux, controlled by the Arbiter Configuration Register SE (snoop enable) bit. If SE is
0, gbl_b will always be negated, and no XLB transaction will be snooped. If SE is 1, the gbl_b signal generated by the master bus interface
will be allowed to pass to the XLB.
For a more detailed description of address snooping and e300 cache-coherency, see the MCP603e Users’ Manual, Section 3.6.
Table 16-13. Arbiter Snoop Window Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
WINBASE[0:15]
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
WINBASE[16:19]
Rsvd
DS
Rsvd
WINSIZE[0:4]
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description
0:19
WINBASE
Window Base Address. Defines the base address of snoopable/non-snoopable addresses for
all PCI, BestComm, and USB address transfers.
20:23
—
Reserved
24
DS
Default Snooping Policy:
0 = Addresses inside window are snooped. Default gbl_b = “negated”
1 = Addresses outside window are snooped. Default gbl_b = “asserted”