Freescale Semiconductor MPC5200B - Manual (Page 747)

MPC5200B Users Guide, Rev. 1
A-8 Freescale Semiconductor
O
O
OC. . . . . . . . . . . . . . . . . . . . . Output Compare
OE . . . . . . . . . . . . . . . . . . . . . Output Enable signal
OEA . . . . . . . . . . . . . . . . . . . Operating Environment Architecture—the level of PowerPC architecture that describes memory
management model, supervisor-level registers, synchronization requirements, and the exception model. It also
defines the time-base feature from a supervisor-level perspective.
OHCI. . . . . . . . . . . . . . . . . . . Open Host Controller Interface—an "Open Host" standard.
Option, Optional . . . . . . . . . . A feature, such as an instruction, register, or exception, defined by the PowerPC architecture, but not required
to be implemented.
OSI . . . . . . . . . . . . . . . . . . . . Open Systems Interconnection
Out-of-order . . . . . . . . . . . . . An aspect of an operation that lets it be performed ahead of one that may have preceded it in the sequential
model. For example, speculative operations. An operation is said to be performed out-of-order if, at the time it
is performed, it is not known to be required by the sequential execution model. See also In-order.
Out-of-order execution . . . . . A technique that lets instructions be issued and completed in an order that differs from their sequence in the
instruction stream.
Overflow . . . . . . . . . . . . . . . . An error condition that occurs during arithmetic operations when the result cannot be stored accurately in the
destination register(s). For example, if two 32-bit numbers are multiplied, the result may not be representable
in 32 bits.
P
Pace control. . . . . . . . . . . . . . Controls the data flow rate between a master and slave.
Page. . . . . . . . . . . . . . . . . . . . A region in memory. The OEA defines a page as a 4KByte area of memory, aligned on a 4KByte boundary.
Page fault . . . . . . . . . . . . . . . A page fault is a condition that occurs when the processor attempts to access a memory location that does not
reside within a page not currently resident in physical memory. On microprocessors that use the PowerPC
architecture, a page fault exception condition occurs when a matching, valid page table entry (PTE[V]=1)
cannot be located.
PCI . . . . . . . . . . . . . . . . . . . . Peripheral Component Interconnect
PCMCIA . . . . . . . . . . . . . . . . Personal Computer Memory Card International Association
PCR. . . . . . . . . . . . . . . . . . . . Peak Cell Rate
PDU . . . . . . . . . . . . . . . . . . . Protocol Data Unit
PHY . . . . . . . . . . . . . . . . . . . Physical Layer Device
Physical memory. . . . . . . . . . The actual memory that can be accessed through the system memory bus.
PIP. . . . . . . . . . . . . . . . . . . . . Parallel Interface Port
Pipelining . . . . . . . . . . . . . . . A technique that breaks operations (such as instruction processing or bus transactions) into smaller distinct
stages or tenures (respectively) so that a subsequent operation can begin before the previous one has completed.
PIT . . . . . . . . . . . . . . . . . . . . Periodic Interrupt Timer
PLL . . . . . . . . . . . . . . . . . . . . Phase-Locked Loop
PM. . . . . . . . . . . . . . . . . . . . . Performance Monitors
PMD . . . . . . . . . . . . . . . . . . . Physical Media-Dependent
POTS. . . . . . . . . . . . . . . . . . . Plain Old Telephone Service—refers to the standard telephone service that most homes use. The main
distinctions between POTS and non-POTS services are speed and bandwidth. POTS is generally restricted to
about 52Kbps. The POTS network is also called the public switched telephone network (PSTN).
PPC . . . . . . . . . . . . . . . . . . . . Port Power Control
PPM . . . . . . . . . . . . . . . . . . . Pulse-Position Modulation
Precise exceptions. . . . . . . . . A category of exception for which the pipeline can be stopped so that instructions preceding the faulting
instruction can complete. Subsequent instructions can then be flushed and redispatched after exception handling
has completed. See also Imprecise exceptions.
pri . . . . . . . . . . . . . . . . . . . . . priority
Primary opcode . . . . . . . . . . . The most-significant 6 bits (bits 0–5) of the instruction encoding that identifies the type of instruction. See also
Secondary opcode.
Protection boundary . . . . . . . A boundary between protection domains.
Protection domain . . . . . . . . . a segment, virtual page, BAT area, or range of unmapped effective addresses. It is defined only when the
appropriate relocate bit in the MSR (IR or DR) is 1.
PSC . . . . . . . . . . . . . . . . . . . . Programmable Serial Controller