Freescale Semiconductor MPC5200B User Manual
Page 340
Registers
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
10-43
10.3.3.2.13 Rx FIFO Alarm Register PCIRFAR(RW) —MBAR + 0x38CC
Bits
Name
Description
0:4
Reserved
Unused. Software shall write zero to these bits. (R/W)
5:7
Granularity
(GR)
Granularity bits control high “watermark” point at which FIFO negates Alarm condition (i.e.,
request for data). It represents the number of free Bytes times 4.
Note: A granularity setting of zero should be avoided because it means the Alarm bit (and
the Requestor signal) will not negate until the FIFO is completely full. The Multi-Channel
DMA module may perform up to 2 additional data writes after the negation of a Requestor
due to its internal pipelining.
Note: This field must be set to a value of 4 or higher. When the FIFO granularity is 0 - 3,
read data can be corrupted with no error indication when the PCI controller simultaneously
writes to the same location that the BestComm is reading from. The workaround is to use a
FIFO granularity of 4 or greater.
8
IP_MASK
Illegal Pointer Mask
When this bit is set, the FIFO controller masks the Status register’s IP bit from generating an
error.
9
FAE_MASK
When this bit is set, the FIFO controller masks the Status Register’s FAE bit from generating
an error.
10
RXW_MASK
When this bit is set, the FIFO controller masks the Status Register’s RXW bit from generating
an error. (To help with backward compatibility, this bit is asserted at reset.)
11
UF_MASK
When this bit is set, the FIFO controller masks the Status Register’s UF bit from generating
an error.
12
OF_MASK
When this bit is set, the FIFO controller masks the Status Register’s OF bit from generating
an error.
13:15
Reserved
Unused. Software should write zero to these bits.
16:31
Reserved
Unused. Software shall write zero to these bits. (R/W)
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
Alarm
Alarm
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:19
Reserved
Unused. Software should write zero to these bits.
20:31
Alarm
[11:0]
User writes these bits to set the low level watermark, which is the point at which the FIFO
asserts its request for data emptying to the Multi-Channel DMA controller. This value is in
bytes. For example, with Alarm = 32, the alarm condition will occur when the FIFO has 32 or
less free bytes in it. The alarm, once asserted, will not negate until the high level mark is
reached, as specified by the Granularity bits in the Rx FIFO Control Register.
Note: The PCI RX FIFO is 512 bytes deep.