Freescale Semiconductor MPC5200B - Manual (Page 470)

I/O Signal Overview
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 14-5
Tx_EN . . . . . . . . . . . . . Assertion of this signal indicates valid nibbles are being presented on the MII. This signal is asserted with the
first nibble of preamble and is negated prior to the first Tx_CLK following the final nibble of the frame.
TxD. . . . . . . . . . . . . . . . TxD[0:3] represent a nibble of data when Tx_EN is asserted and have no meaning when Tx_EN is de-asserted.
Table 14-2 summarizes the permissible encoding of TxD.
Tx_ER . . . . . . . . . . . . . Assertion of this signal for one or more clock cycles while Tx_EN is asserted causes PHY to transmit one or
more illegal symbols. Asserting Tx_ER has no affect when operating at 10 Mbps or when Tx_EN is de-asserted
This signal transitions synchronously with respect to Tx_CLK.
Rx_DV . . . . . . . . . . . . . When this signal is asserted, PHY is indicating a valid nibble is present on the MII. This signal remains asserted
from the first recovered nibble of the frame through the last nibble. Assertion of Rx_DV must start no later than
the SFD, and exclude any EOF.
RxD. . . . . . . . . . . . . . . . RxD[0:3] represents a nibble of data to be transferred from the PHY to the MAC when Rx_DV is asserted. A
completely formed SFD must be passed across the MII. When Rx_DV is not asserted, RxD has no meaning.
There is an exception to this which is explained later.
Table 14-3 summarizes the permissible encoding of RxD.
Rx_ER . . . . . . . . . . . . . When Rx_ER and Rx_DV are asserted, the PHY has detected an error in the current frame.
When Rx_DV is not asserted, Rx_ER shall have no affect. This signal transitions synchronously with Rx_CLK.
CRS . . . . . . . . . . . . . . . Signal is asserted when Tx or Rx medium is not idle. If a collision occurs, CRS remains asserted through the
duration of the collision. This signal is not required to transition synchronously with Tx_CLK or Rx_CLK.
COL . . . . . . . . . . . . . . . Signal is asserted on a collision detection and remains asserted while the collision persists. The signal behavior
is not specified when in full-duplex mode. This signal is not required to transition synchronously with Tx_CLK
or Rx_CLK.
MDC. . . . . . . . . . . . . . . Signal provides a timing reference to the PHY for data transfers on the MDIO signal. MDC is aperiodic and has
no maximum high or low times. The minimum high and low times is 160 ns with the minimum period being
400 ns.
MDIO . . . . . . . . . . . . . . Signal transfers control/status information between the PHY and MAC. It transitions synchronously to MDC.
The MDIO pin is a bidirectional pin. The internal FEC signals that connect to this pad are: MDI (data in), MDO
(data out) and MD_EN (direction control, high for output).
Table 14-2 lists the interpretation of possible encodings for Tx_EN and Tx_ER.
A false carrier condition occurs if the PHY detects a bad start-of-stream delimiter. This condition signals the MII by asserting Rx_ER and
placing 1110 on RxD. Rx_DV must also be de-asserted. Valid Rx_DV, Rx_ER and RxD[3:0] encodings are shown in
Table 14-3 .
14.3.1.2 MII Management Frame Structure
A transceiver management frame transmitted on the MII management interface uses the MDIO and MDC pins. A transaction or frame on this
serial interface has the following format: - <preamble><st><op><phyad><regad><ta><data><idle>
Table 14-2. MII: Valid Encoding of TxD, Tx_EN and Tx_ER
TX_EN TX_ER TXD Indication
0 0 0000 through 1111 Normal inter-frame
0 1 0000 through 1111 Reserved
1 0 0000 through 1111 Normal data transmission
1 1 0000 through 1111 Transmit error propagation
Table 14-3. MII: Valid Encoding of RxD, Rx_ER and Rx_DV
RX_DV RX_ER RXD Indication
0 0 0000 through 1111 Normal inter-frame
0 1 0000 Normal inter-frame
0 1 0001 through 1101 Reserved
0 1 1110 False Carrier
0 1 1111 Reserved
1 0 0000 through 1111 Normal data reception
1 1 0000 through 1111 Data reception with errors