Freescale Semiconductor MPC5200B - Manual (Page 674)

Functional Description
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 19-35
19.7.8.1 CPU Run Mode
As can be seen in Table 19-35 , only MSCAN Sleep Mode is available as low power option, when CPU is in run mode.
19.7.8.2 CPU Sleep Mode
While the CPU is in Sleep Mode, the MSCAN can be operated in Normal Mode and generate interrupts (registers can be accessed via
background debug mode). The MSCAN can also operate in any of the low power modes depending on the values of the SLPRQ/SLPAK and
CSWAI bits as seen in
Table 19-35 .
19.7.8.3 CPU Deep Sleep Mode
In Deep Sleep Mode, the MSCAN operates in Power Down mode regardless of the value of the SLPRQ/SLPAK and CSWAI bits Table 19-35 .
19.7.8.4 MSCAN Sleep Mode
The CPU can request the MSCAN to enter this low power mode by asserting the SLPRQ bit in the CANCTL0 register. The time when the
MSCAN enters Sleep Mode depends on a fixed synchronization delay and its current activity:
• If it is transmitting, it continues to transmit until the entire message is transmitted and then goes into Sleep Mode.
• If it is receiving, it waits for the end of this message and then goes into Sleep Mode.
• If it is neither transmitting nor receiving, it immediately goes into Sleep Mode.
Figure 19-9. Sleep Request / Acknowledge Cycle
NOTE
The application software must avoid setting up a transmission (by clearing one or more TXEx flag(s))
and immediately request Sleep Mode (by setting SLPRQ). It depends on the exact sequence of
operations whether the MSCAN starts transmitting or goes into Sleep Mode directly.
If Sleep Mode is active, the SLPRQ and SLPAK bits are set ( Figure 19-9 ). The application software must use SLPAK as a handshake
indication for the request (SLPRQ) to go into Sleep Mode.
When in Sleep Mode (SLPRQ=1 and SLPAK=1), the MSCAN stops its internal clocks. However, clocks to allow register accesses from the
CPU side still run. If the MSCAN is in Bus-Off state, it stops counting the 128*11 consecutive recessive bits due to the stopped clocks. The
TXCAN pin remains in a recessive state. If RXF=1, the message can be read and RXF can be cleared. Shifting a new message into the
foreground buffer of the receiver FIFO (RxFG) does not take place while in Sleep Mode. It is possible to access the transmit buffers and to
clear the associated TXE flags. No message abort takes place while in Sleep Mode. If the WUPE bit in CANCLT0 is not asserted, the MSCAN
will mask any activity it detects on CAN. The RXCAN pin is therefore held internally in a recessive state. This locks the MSCAN in Sleep
Mode (
Section Figure 19-10., Simplified State Transitions for Entering/Leaving Sleep Mode ).
The MSCAN is only able to leave Sleep Mode (wake-up) when
• bus activity occurs and WUPE=1 or
• the MCU clears the SLPRQ bit
a
‘X’ means don’t care.
SYNC
SYNC
CPU Clock Domain CAN Clock Domain
MSCAN
in Sleep Mode
CPU
Sleep Request
SLPRQ
Flag
SLPAK
Flag
SLPRQ
sync.
SLPAK
sync.
SLPRQ
SLPAK