Freescale Semiconductor MPC5200B - Manual (Page 644)

Memory Map / Register Definition
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 19-5
19.5.2 Register Descriptions
This section describes in detail all the registers and register bits in the MSCAN module. Each description includes a standard register diagram
with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. All bits of all registers in
this module are completely synchronous to internal clocks during a register read.
The registers are located at an offset from MBAR of 0x0900 (MSCAN1) and 0x0980 (MSCAN2) . Register addresses are relative to this
offset.
19.5.3 MSCAN Control Register 0 (CANCTL0)—MBAR + 0x0900 / 0x980
The MSCAN Control Register 0, CANCTL0, provides for various control of the MSCAN Module.
NOTE: The MSCAN Control Register 0, except the WUPE, INITRQ and SLPRQ bits, is held in the reset state when the Initialization Mode
is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the Initialization Mode is exited (INITRQ = 0 and INITAK
= 0).
Read: Anytime
Write: Anytime when out of Initialization; exceptions are bits RXACT and SYNCH which are read-only and bit RXFRM which is set by the
module. A write of ‘1’ to the RXFRM register clears the flag and a write of ‘0’ is ignored.
$__35,$__B5 MSCAN Identifier Acceptance Register 7 (CANIDAR7) R/W
$__38,$__B8 MSCAN Identifier Mask Register 4 (CANIDMR4) R/W
$__39,$__B9 MSCAN Identifier Mask Register 5 (CANIDMR5) R/W
$__3C,$__BC MSCAN Identifier 6 Mask Register 6 (CANIDMR6) R/W
$__3D,$__BD MSCAN Identifier Mask Register 7 (CANIDMR7) R/W
$__40 -$__5F,
$__C0 -$__DF
Foreground Receive Buffer (CANRXFG) R b
$__60 -$__7F,
$__E0 -$__FF Foreground Transmit Buffer (CANTXFG) R
2
/W
a Refer to detailed register description for write access restrictions on per bit basis.
b Reserved bits and unused bits within the TX- & RX-Buffers (CANTXFG, CANRXFG) will be read
as “X”, because of RAM based implementation.
Table 19-3. MSCAN Control Register 0
msb 0 1 2 3 4 5 6 7 lsb
R
RX
F
R
M
RXA
C
T
CSW
A
I
SYNCH
TI
ME
WUPE SLPR
Q
IN
IT
R
Q
W
RESET: 0 0 0 0 0 0 0 1
Table 19-2. Module Memory Map (continued)