9 cdm soft reset register-mbar + 0x0220, 10 cdm system pll status register-mbar + 0x0224, Cdm soft reset register – Freescale Semiconductor MPC5200B User Manual
Page 153: Cdm system pll status register
MPC5200B Users Guide, Rev. 1
5-20
Freescale Semiconductor
CDM Registers
5.5.9
CDM Soft Reset Register—MBAR + 0x0220
This register contains 2 reset control bits.
5.5.10
CDM System PLL Status Register—MBAR + 0x0224
This register contains control and status bits of the CDM PLL lock detect module.
Table 5-16. CDM Soft Reset Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
Write 0
cdm_soft
_reset
Reserved
Write 0
cdm_no_
ck
s
tp
_
re
s
e
t
W
RESET:
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
Write 0
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description
0–6
—
Reserved for future use. Write 0.
7
cdm_soft_reset
CDM Soft Reset bit.
bit=0:requests CDM soft reset.
bit=1:CDM soft reset request inactive.
8–14
—
Reserved for future use. Write 0.
15
cdm_no_ckstp_reset
CDM No reset on checkstop.
bit=0:Checkstop assertion causes HRESET.
bit=1:Checkstop assertion does not cause HRESET.
16–31
—
Reserved for future use. Write 0.
Table 5-17. CDM System PLL Status Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
Write 0
pl
l_loc
k
Reserved
Write 0
pl
l_
los
t
_loc
k
W
RESET:
0
0
0
0
0
0
0
—
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
Write 0
pll_small_
lo
c
k
_windo
w
Reserved
Write 0
W
RESET:
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0