Freescale Semiconductor MPC5200B - Manual (Page 650)

Memory Map / Register Definition
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 19-11
Bit Name Description
0 WUPIF WakeUp Interrupt Flag—If MSCAN detects bus activity while in sleep mode and WUPE=1
in CANTCTL0, it sets the WUPIF flag. If not masked, a WakeUp interrupt is pending while
this flag is set.
0 = No WakeUp activity observed while in Sleep Mode.
1 = MSCAN detected bus activity and requested WakeUp.
1 CSCIF CAN Status Change Interrupt Flag—flag is set when MSCAN changes its current bus
status due to actual value of Tx error counter (TEC) and Rx error counter (REC). An
additional 4-bit (RSTAT[1:0], TSTAT[1:0]) status register, split into separate sections for
TEC/REC, notifies system of actual bus status.
If not masked, an error interrupt is pending while this flag is set. CSCIF provides a blocking
interrupt. That guarantees the Rx/Tx status bits (RSTAT/TSTAT) are updated only when
no CAN Status Change interrupt is pending.
If TECs/RECs change their current value after CSCIF is asserted and therefore cause an
additional state change in RSTAT/TSTAT bits, these bits keep their old state bits until the
current CSCIF interrupt is again cleared.
0 = No change in bus status occurred since last interrupt
1 = MSCAN changed current bus status.
2:3 RSTAT[1:0] Receiver Status bits—values of the error counters control the actual bus status of the
MSCAN. As soon as the status change interrupt flag (CSCIF) is set these bits indicate the
appropriate receiver related bus status of the MSCAN. The coding for the bits RSTAT1,
RSTAT0 is:
00 = RxOK: 0
≤ Receive Error Counter ≤ 96
01 = RxWRN: 96 < Receive Error Counter
≤ 127
10 = RxERR: 127 < Receive Error Counter
11 = BusOff: Transmit Error Counter > 255
Note: Redundant Information for the most critical bus status which is CAN Bus-Off. This
only occurs if the Tx Error Counter exceeds a number of 255 errors. CAN Bus-Off affects
the receiver state. As soon as the transmitter leaves its Bus-Off state the receiver state
skips to RxOK too. Refer also to TSTAT[1:0] coding.
4:5 TSTAT[1:0] Transmitter Status bits—values of the error counters control the actual bus status of the
MSCAN. As soon as the status change interrupt flag (CSCIF) is set these bits indicate the
appropriate transmitter related bus status of the MSCAN. The coding for the bits TSTAT1,
TSTAT0 is:
00 = TxOK: 0
≤ Transmit Error Counter ≤ 96
01 = TxWRN: 96 < Transmit Error Counter
≤ 127
10 = TxERR: 127 < Transmit Error Counter
≤ 255
11 = BusOff: Transmit Error Counter > 255
6 OVRIF Overrun Interrupt Flag—flag is set when a data overrun condition occurs. If not masked,
an Error interrupt is pending while this flag is set.
0 = No data overrun condition.
1 = data overrun detected.