Freescale Semiconductor MPC5200B - Manual (Page 726)

Functional Description
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 20-47
Figure 20-19. Basic BDLC Module Transmit Flowchart
20.8.9 BDLC Module Initialization
This section includes sample flows for initializing the BDLC module and using it to transmit and receive messages.
20.8.9.1 Initialization Sequence
To initialize the BDLC module, the user should first write the desired data to the configuration bits. The BDLC module should then be taken
out of digital and analog loopback mode and enabled. Exiting from loopback mode will entail change of state indications in the BDLC State
Vector Register which must be dealt with. Once this is complete, CPU interrupts can be enabled (if desired), and then the BDLC module is
capable of SAE J1850 serial network communication. For an illustration of the sequence necessary for initializing the BDLC module, refer
to
Figure 20-20 .
Enter BDLC module Transmit
Routine
Write first message
byte to be transmitted
into DLCBDR
Is DLCBSVR = $00?
Yes
No
Load next byte to be
transmitted into DLCBDR
(clears TDRE)
Is DLCBSVR = $1C?
Yes
No
Is DLCBSVR = $14?
Yes
No
Is DLCBSVR = $10?
Yes
No
(TDRE)
(LOA)
(Invalid Symbol)
Attempt another
Yes
No
transmission?
Is this the last
Yes
No
byte?
A
A
Jump to BDLC module
Receive Routine
Once BDLC module detects
EOF, transmit
Set TEOD bit
in DLCBCR2
attempt is complete
Yes
No
IFR Received?
Jump to Receive IFR
Handling Routine
Exit BDLC module Transmit
Routine
B
B
C
C
Go to BDLC module
BREAK/Error Handling
Routine
For interrupt driven systems,
this marks the beginning of the
transmit section of the BDLC
module interrupt service
routine
NOTE: The EOF and CRC Error interrupts
are handled in the BDLC module Receive
Routine