Freescale Semiconductor MPC5200B - Manual (Page 385)

MPC5200B Users Guide, Rev. 1
11-20 Freescale Semiconductor
ATA Host Controller Operation
11.4 ATA Host Controller Operation
With the asynchronous ATA interface, an interface must be implemented that meets the timing specifications, given an input clock from the
processor that is not fixed among all applications. The challenge is to meet the minimum ATA specifications while minimizing wasted time.
Time is wasted because of differences between the minimum specification and the number of clock-cycles, multiplied by the clock-cycle
period. This indicates the counter compare value depends on:
• the data transfer mode
• the clock frequency driving the ATA state machine (IPB clock)
• the minimum data transfer mode cycle-time passed in the INDENTIFY block from the drive to the ATA Host Controller
Software requirements for setting up the Host Controller are as follows:
1. Write into ata_config register to enable (ata_config[7] == 1) support for IORDY for PIO modes 3 and 4.
2. Software determines ATA mode timing based on the operating clock frequency
This rounds up to the smallest integer number of clock counts that meet the minimum specification.
In the case of counters that control duration of a read strobe (pio_t2_8, pio_t2_16 and dma_td), the added transceiver propagation
delay must be taken into account so the read data meets setup time to the rising edge of the strobe. Therefore:
12 IE Enables drive interrupt to pass to CPU in DMA/UDMA modes. Software writes to this register
as follows:
• FE (bit 11) and IE (bit 12)
• Clear IE and set FE if SDMA task loop count is the same as the data transfer requested
from the drive.
The following is a typical sequence if the SDMA task loop is a larger count than data request
programmed for the drive:
1. Start transaction with IE set and FE cleared.
2. Repeat 1 until task loop count expires.
3. Start last transaction with IE clear and FE set.
• Controller issues flush at end.
• Task loop completes and interrupts CPU.
• CPU responds to BestComm interrupt instead of drive interrupt.
• UDMA (bit 13)—Set when UDMA protocol is selected for data transfer, cleared for DMA
protocol.
• READ (bit 14)—Set when read command for DMA/UDMA protocols is written to drive
command register, cleared otherwise.
• WRITE (bit 15)—Set when write command for DMA/UDMA protocols is written to drive
command register, cleared otherwise.
MANDATORY—Be Aware: Drive interrupt must be enabled by clearing bit 1 of drive control
register for DMA/UDMA mode transfers.
13 UDAMA Bit is set when UDMA protocol is selected, cleared when multiword DMA protocol is selected.
14 READ Bit is set when READ DMA command is issued.
15 WRITE Bit is set when WRITE DMA command is issued.
16:31 — Reserved
Bits Name Description
Count
ATA_mode_timing_spec ipbi_clock_period 1 – +
clock_period
------------------------------------------------------------------------------------------------------------------------ =
Count
ATA_mode_timing_spec 2 XCVR_PROP_DLY clock_period 1 – + × +
clock_period
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- =