Freescale Semiconductor MPC5200B - Manual (Page 360)

Application Information
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 10-63
The PCI Arbiter implements a Round-Robin fairness algorithm, which avoids the domination of the bus by high-priority masters and
exclusion of low-priority masters. The PCI Arbiter is capable of Parking the current Master to stay on last master in absence of other requests.
The support of the non-PCI clients presents special challenges to the arbitration scheme.
The PCI Arbiter runs independently. The programmability consists of a Soft Reset, which allows to reset the PCI Arbiter, and one status bit
to detect the Broken Master condition. and a corresponding enable bit for the generation of a CPU interrupt for the Broken Master condition.
All these register bits are located in registers of the PCI Controller.
In case of broken master detection the external PCI REQ# will be dis-connected internally and will be re-connected after external deassertion
of PCI REQ# or by software (Softreset) or by Hardreset. After broken master detection (bus idle for 16 clocks) the arbiter will ignore any PCI
FRAME# assertion.
The PCI Arbiter does not support preemption of the internal masters XIPCI or SCPCI. The internal master is granted until the transaction has
been completed. The Latency Timer (LT) cannot terminate any transfer.
10.6 Application Information
This section provides example usage of some of the features of the PCI module.
10.6.1 XL bus Initiated Transaction Mapping
The use of the PCI Configuration Address Register along with the initiator window registers provide many possibilities for PCI command and
address generation.
Table 10-15 shows how the PCI Controller accepts read and write requests from a XLB bus master and decodes them to
different address ranges resulting in the generation of memory, I/O, configuration, interrupt acknowledge and special cycles on the PCI bus.
The Window Registers are defined in
Section 10.3.2.6, Initiator Window 1 Base/Translation Address Register PCIIW1BTAR(RW) —MBAR +
0x0D74 through Section 10.3.2.8, Initiator Window Configuration Register PCIIWCR(RW) —MBAR + 0x0D80 .
Table 10-15. Transaction Mapping: XL Bus -> PCI
XL bus Transaction
(XL Bus Slave Interface)
Cache Line
Size
Register=
8
Initiator Register Settings
PCI Transaction
Controller (XL Bus
Initiator Interface) ->
PCI Target
Initiator Window
Configuration bits
Configuration
Address
Register
IO/M# PRC En
device
number
==
b1_1111
Single-Beat 1 -> 8 byte Read x 0 b00 x x Memory Read
Burst Read (32 bytes) x 0 b00 x x Memory Read
Single-Beat 1 -> 8 byte Read x 0 b01 x x Memory Read
Burst Read false 0 b01 x x Memory Read
Burst Read true 0 b01 x x Memory Read Line
Single-Beat 1 -> 8 byte Read x 0 b10 x x Memory Read Multiple
Burst Read x 0 b10 x x Memory Read Multiple
Single-Beat 1 -> 8 byte, or Burst
Write x 0 x x x Memory Write
Single-Beat 1 -> 4 byte Read x 1 x 0 x I/O Read
Single-Beat 1 -> 4 byte Write x 1 x 0 x I/O Write
Single-Beat 1 -> 4 byte Read x 1 x 1 false Configuration Read
Single-Beat 1 -> 4 byte Write x 1 x 1 false Configuration Write
Single-Beat 1 -> 4 byte Read x 1 x 1 true Interrupt acknowledge