Freescale Semiconductor MPC5200B - Manual (Page 704)

Functional Description
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 20-25
• Valid BREAK Symbol
If the next active to passive transition does not occur until after T
rv6(Min)
, the current symbol will be considered a valid BREAK
symbol. A BREAK symbol should be followed by a SOF symbol beginning the next message to be transmitted onto the J1850 bus.
See
Figure 20-9 .
• Message Arbitration
Message arbitration on the J1850 bus is accomplished in a non-destructive manner, allowing the message with the highest priority
to be transmitted, while any transmitters which lose arbitration simply stop transmitting and wait for an idle bus to begin transmitting
again.
If the BDLC module wishes to transmit onto the J1850 bus, but detects that another message is in progress, it automatically waits
until the bus is idle. However, if multiple nodes begin to transmit in the same synchronization window, message arbitration will
occur beginning with the first bit after the SOF symbol and continue with each bit thereafter.
The VPW symbols and J1850 bus electrical characteristics are carefully chosen so that a logic zero (active or passive type) will
always dominate over a logic one (active or passive type) simultaneously transmitted. Hence logic zeroes are said to be ‘dominant’
and logic ones are said to be ‘recessive’.
Whenever a node transmits a recessive bit and detects a dominant bit, it loses arbitration, and immediately stops transmitting. This
is known as ‘bitwise arbitration’.The loss of arbitration flag (in BDLC State Vector Register) is set when arbitration is lost. If the
interrupt enable bit (IE in BDLC Control Register 1) is set, an interrupt request from the BDLC module is generated. Reading the
BDLC State Vector Register register will clear this flag.
Figure 20-10. J1850 VPW Bitwise Arbitrations
During arbitration, or even throughout the transmitting message, when an opposite bit is detected, transmission is immediately
stopped unless it occurs on the 8th bit of a byte. In this case the BDLC module will automatically append up to two extra 1 bits and
then stop transmitting. These two extra bits will be arbitrated normally and thus will not interfere with another message. The second
1 bit will not be sent if the first loses arbitration. If the BDLC module has lost arbitration to another valid message then the two extra
ones will not corrupt the current message. However, if the BDLC module has lost arbitration due to noise on the bus, then the two
extra ones will ensure that the current message will be detected and ignored as a noise-corrupted message.
Since a “0” dominates a “1”, the message with the lowest value will have the highest priority, and will always win arbitration, i.e.
a message with priority 000 will win arbitration over a message with priority 011. This method of arbitration will work no matter
how many bits of priority encoding are contained in the message.
Transmitter A
Transmitter B
J1850 Bus
SOF
Data
Bit 1
Data
Bit 4
Data
Bit 5
“0”
Transmitter A detects
an active state on
the bus, and stops
transmitting
Transmitter B wins
Passive
Active
Passive
Active
Passive
Active
“0”
“0”
“1”
“1”
“1”
Data
Bit 2
“1”
“1”
“1”
Data
Bit 3
“0”
“0”
“0”
“0”
“1”
arbitration and
continues
transmitting